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1. 发明授权

US08610181B2 V-groove source/drain MOSFET and process for fabricating same 有权
标题翻译： V沟槽源极/漏极MOSFET及其制造工艺
公开(公告)号：US08610181B2
公开(公告)日：2013-12-17
申请号：US13624251
申请日：2012-09-21
申请人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
发明人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/085
CPC分类号： H01L21/823425 , H01L21/823481 , H01L21/84 , H01L29/045 , H01L29/41733 , H01L29/458 , H01L29/66772
摘要： A structure includes a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate and a silicided source/drain region formed in a V-shaped groove between the first and second adjacent gate structures. The silicided source/drain region formed in the V-shaped groove extend substantially from an edge of the first gate structure to an opposing edge of the second gate structure.
摘要翻译：一种结构包括在衬底的硅表面上至少包含第一和第二相邻栅极结构的衬底和形成在第一和第二相邻栅极结构之间的V形沟槽中的硅化物源/漏极区。形成在V形槽中的硅化物源极/漏极区域基本上从第一栅极结构的边缘延伸到第二栅极结构的相对边缘。

2. 发明授权

US08603868B2 V-groove source/drain MOSFET and process for fabricating same 有权
标题翻译： V沟槽源极/漏极MOSFET及其制造工艺
公开(公告)号：US08603868B2
公开(公告)日：2013-12-10
申请号：US13329604
申请日：2011-12-19
申请人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
发明人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L21/782
CPC分类号： H01L21/823425 , H01L21/823481 , H01L21/84 , H01L29/045 , H01L29/41733 , H01L29/458 , H01L29/66772
摘要： A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.
摘要翻译：一种方法包括在衬底的硅表面上提供至少包含第一和第二相邻栅极结构的衬底; 蚀刻通过所述第一和第二相邻栅极结构之间的所述硅表面的V形槽，其中所述V形槽基本上从所述第一栅极结构的边缘延伸到所述第二栅极结构的相对边缘; 将源极/漏极区域注入到V形沟槽中; 并且将植入的源极/漏极区域硅化。蚀刻步骤优选通过使用停止在硅衬底（例如，SOI层）的Si（111）平面上的基于HCl的化学气相蚀刻（CVE）进行。还公开了根据该方法制造的包含FET的结构。

3. 发明申请

US20130153971A1 V-GROOVE SOURCE/DRAIN MOSFET AND PROCESS FOR FABRICATING SAME 有权
标题翻译： V沟道源/漏极MOSFET及其制造方法
公开(公告)号：US20130153971A1
公开(公告)日：2013-06-20
申请号：US13329604
申请日：2011-12-19
申请人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
发明人： Michael A. Guillorn , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H01L21/823425 , H01L21/823481 , H01L21/84 , H01L29/045 , H01L29/41733 , H01L29/458 , H01L29/66772
摘要： A method includes providing a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate; etching a V-shaped groove through the silicon surface between the first and second adjacent gate structures, where the V-shaped groove extends substantially from an edge of the first gate structure to an opposing edge of the second gate structure; implanting a source/drain region into the V-shaped groove; and siliciding the implanted source/drain region. The etching step is preferably performed by using a HCl-based chemical vapor etch (CVE) that stops on a Si(111) plane of the silicon substrate (e.g., a SOI layer). A structure containing FETs that is fabricated in accordance with the method is also disclosed.
摘要翻译：一种方法包括在衬底的硅表面上提供至少包含第一和第二相邻栅极结构的衬底; 蚀刻通过所述第一和第二相邻栅极结构之间的所述硅表面的V形槽，其中所述V形槽基本上从所述第一栅极结构的边缘延伸到所述第二栅极结构的相对边缘; 将源极/漏极区域注入到V形沟槽中; 并且将植入的源极/漏极区域硅化。蚀刻步骤优选通过使用在硅衬底（例如，SOI层）的Si（111）平面上停止的基于HCl的化学气相蚀刻（CVE）进行。还公开了根据该方法制造的包含FET的结构。

4. 发明申请

US20140073106A1 LATERAL BIPOLAR TRANSISTOR AND CMOS HYBRID TECHNOLOGY 审中-公开
标题翻译：横向双极晶体管和CMOS混合技术
公开(公告)号：US20140073106A1
公开(公告)日：2014-03-13
申请号：US13610961
申请日：2012-09-12
申请人： Josephine B. Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L21/331
CPC分类号： H01L29/66265 , H01L21/84 , H01L29/6625 , H01L29/7317
摘要： A method of forming a lateral bipolar transistor. The method includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.
摘要翻译：一种形成横向双极晶体管的方法。该方法包括形成具有底部衬底层的绝缘体上硅（SOI）衬底，在衬底层顶部上的掩埋氧化物层（BOX）以及BOX层顶部上的绝缘体上硅（SOI）层，形成在绝缘体上硅层的顶部设置虚拟栅极和间隔物，用正离子或负离子掺杂SOI层，使用化学机械平面化（CMP）沉积层间电介质（ILD）以平坦化ILD，去除伪栅极，从而形成栅极沟槽，其显示虚拟栅极的基极，掺杂伪栅极基底，在SOI层的顶部上沉积多晶硅层并进入栅极沟槽，蚀刻多晶硅层，使得其仅覆盖伪栅极基极，以及应用自对准硅化物工艺。

5. 发明申请

US20120256242A1 SEMICONDUCTOR NANOWIRE STRUCTURE REUSING SUSPENSION PADS 有权
标题翻译：半导体纳米结构复原悬挂垫
公开(公告)号：US20120256242A1
公开(公告)日：2012-10-11
申请号：US13080390
申请日：2011-04-05
申请人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/86 , B82Y99/00 , B82Y40/00
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
摘要翻译：提供一种集成电路装置，其包括形成在绝缘体基板上的第一和第二绝缘体上硅（SOI）焊盘，第一和第二SOI焊盘中的每一个包括形成在其上的有源区，悬挂在第一和第二SOI之间的纳米线绝缘体衬底上的衬垫，沿着纳米线可操作地设置的一个或多个场效应晶体管（FET）和可操作地设置在形成在每个第一和第二SOI衬垫上的相应有源区域中的至少一个上的平面器件。

6. 发明申请

US20170194509A1 WIRE-LAST GATE-ALL-AROUND NANOWIRE FET 审中-公开
公开(公告)号：US20170194509A1
公开(公告)日：2017-07-06
申请号：US15180314
申请日：2016-06-13
申请人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/786 , H01L29/423 , H01L29/66 , H01L29/06
CPC分类号： H01L29/78696 , H01L21/0217 , H01L21/02381 , H01L21/02532 , H01L21/30604 , H01L21/324 , H01L29/0673 , H01L29/165 , H01L29/401 , H01L29/42376 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/775 , H01L29/78618
摘要： A nanowire field effect transistor (FET) device includes a first source/drain region and a second source/drain region. Each of the first and second source/drain regions are formed on an upper surface of a bulk semiconductor substrate. A gate region is interposed between the first and second source/drain regions, and directly on the upper surface of the bulk semiconductor substrate. A plurality of nanowires are formed only in the gate region. The nanowires are suspended above the semiconductor substrate and define gate channels of the nanowire FET device. A gate structure includes a gate electrode formed in the gate region such that the gate electrode contacts an entire surface of each nanowire.

7. 发明授权

US08853790B2 Semiconductor nanowire structure reusing suspension pads 有权
标题翻译：半导体纳米线结构重用悬挂垫
公开(公告)号：US08853790B2
公开(公告)日：2014-10-07
申请号：US13080390
申请日：2011-04-05
申请人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
发明人： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L51/48 , H01L29/786 , H01L27/12 , H01L29/06 , B82Y10/00 , H01L29/423 , H01L21/84
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： An integrated circuit apparatus is provided and includes first and second silicon-on-insulator (SOI) pads formed on an insulator substrate, each of the first and second SOI pads including an active area formed thereon, a nanowire suspended between the first and second SOI pads over the insulator substrate, one or more field effect transistors (FETs) operably disposed along the nanowire and a planar device operably disposed on at least one of the respective active areas formed on each of the first and second SOI pads.
摘要翻译：提供一种集成电路装置，其包括形成在绝缘体基板上的第一和第二绝缘体上硅（SOI）焊盘，第一和第二SOI焊盘中的每一个包括形成在其上的有源区，悬挂在第一和第二SOI之间的纳米线绝缘体衬底上的衬垫，沿着纳米线可操作地设置的一个或多个场效应晶体管（FET）和可操作地设置在形成在每个第一和第二SOI衬垫上的相应有源区域中的至少一个上的平面器件。

8. 发明授权

US07893492B2 Nanowire mesh device and method of fabricating same 有权
标题翻译：纳米线网装置及其制造方法
公开(公告)号：US07893492B2
公开(公告)日：2011-02-22
申请号：US12371943
申请日：2009-02-17
申请人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Stephen W. Bedell , Josephine B. Chang , Paul Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/02
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66772 , H01L29/66795 , H01L29/775 , H01L29/785 , H01L29/78696 , Y10S977/72 , Y10S977/742 , Y10S977/762 , Y10S977/938
摘要： A semiconductor structure is provided that includes a plurality of vertically stacked and vertically spaced apart semiconductor nanowires (e.g., a semiconductor nanowire mesh) located on a surface of a substrate. One end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a source region and another end segment of each vertically stacked and vertically spaced apart semiconductor nanowires is connected to a drain region. A gate region including a gate dielectric and a gate conductor abuts the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, and the source regions and the drain regions are self-aligned with the gate region.
摘要翻译：提供一种半导体结构，其包括位于衬底表面上的多个垂直堆叠且垂直间隔开的半导体纳米线（例如，半导体纳米线网）。每个垂直堆叠和垂直间隔开的半导体纳米线的一个端段连接到源极区域，并且每个垂直堆叠和垂直间隔开的半导体纳米线的另一个端部段连接到漏极区域。包括栅极电介质和栅极导体的栅极区域邻接多个垂直堆叠和垂直间隔的半导体纳米线，并且源极区域和漏极区域与栅极区域自对准。

9. 发明授权

US08703576B2 Gap-fill keyhole repair using printable dielectric material 失效
公开(公告)号：US08703576B2
公开(公告)日：2014-04-22
申请号：US13232293
申请日：2011-09-14
申请人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L21/76
CPC分类号： H01L29/51 , H01L21/311 , H01L21/76825 , H01L21/76837 , H01L29/66545
摘要： Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities. The gate cavities are filled with a gate dielectric and a gate electrode.

10. 发明申请

US20130062709A1 Gap-Fill Keyhole Repair Using Printable Dielectric Material 失效
标题翻译：使用可印刷介质材料进行缺陷孔眼修复
公开(公告)号：US20130062709A1
公开(公告)日：2013-03-14
申请号：US13232293
申请日：2011-09-14
申请人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Paul Chang , Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L29/51 , H01L21/28
CPC分类号： H01L29/51 , H01L21/311 , H01L21/76825 , H01L21/76837 , H01L29/66545
摘要： Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities. The gate cavities are filled with a gate dielectric and a gate electrode.
摘要翻译：在半导体衬底上形成一次性栅极结构。平坦化电介质层沉积在一次性栅极结构上并且被平坦化以提供与一次性栅极结构的顶表面共面的顶表面。此时的平坦化电介质层包括狭缝间隔一次性栅极结构之间的间隙填充键孔。在平坦化介电层上沉积可印刷介电层以填充间隙填充键孔。在间隙填充键孔上的可印刷电介质层的区域被可印刷介电层的材料中交叉连接的辐射辐射照射。可打印介电层的非交联部分随后被选择性地移除到可印刷介电层的交联部分，该可印刷电介质层至少填充每个栅极填充孔眼的上部。去除一次性门结构以形成门腔。栅极腔填充有栅极电介质和栅电极。

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