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1. 发明授权

US08617957B1 Fin bipolar transistors having self-aligned collector and emitter regions 失效
标题翻译：鳍状双极晶体管具有自对准的集电极和发射极区域
公开(公告)号：US08617957B1
公开(公告)日：2013-12-31
申请号：US13607877
申请日：2012-09-10
申请人： Josephine B Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W Sleight
发明人： Josephine B Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W Sleight
IPC分类号： H01L21/331
CPC分类号： H01L29/42304 , H01L29/1008 , H01L29/6625 , H01L29/66265 , H01L29/7317 , H01L29/735 , H01L29/785
摘要： A method for fabricating a bipolar transistor device. The method includes the steps of: providing a SOI substrate having a silicon layer thereon; patterning lithographically a fin hardmask on the silicon layer; placing a dummy contact line over a central portion of patterned fin hardmask; doping the collector/emitter regions; depositing a filler layer over the collector region and the emitter region; removing the dummy contact line to reveal a trench and the central portion of the patterned fin hardmask; forming fin-shaped base regions by removing, within the trench, a portion of the silicon layer not covered by the central portion of the patterned fin hardmask after the step of removing the dummy contact line; doping the fin-shaped base region; and forming a contact line by filling the trench with a contact line material over the fin-shaped base regions, where the collector/emitter regions are self-aligned with the contact line.
摘要翻译：一种制造双极晶体管器件的方法。该方法包括以下步骤：提供其上具有硅层的SOI衬底; 在硅层上平版印刷鳍状硬掩模; 将虚拟接触线放置在图案化翅片硬掩模的中心部分上; 掺杂集电极/发射极区域; 在所述集电极区域和所述发射极区域上沉积填充层; 去除虚拟接触线以露出沟槽和图案化散热片硬掩模的中心部分; 在除去虚拟接触线的步骤之后，通过在沟槽内去除未被图案化翅片硬掩模的中心部分覆盖的硅层的一部分来形成翅片形基底区域; 掺杂鳍片状基底区域; 以及通过在所述鳍状基极区域上的接触线材料填充所述沟槽而形成接触线，其中所述集电极/发射极区域与所述接触线自对准。

2. 发明授权

US08618636B1 Fin bipolar transistors having self-aligned collector and emitter regions 有权
公开(公告)号：US08618636B1
公开(公告)日：2013-12-31
申请号：US13609615
申请日：2012-09-11
申请人： Josephine B Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W Sleight
发明人： Josephine B Chang , Gen Pei Lauer , Isaac Lauer , Jeffrey W Sleight
IPC分类号： H01L29/66
CPC分类号： H01L29/42304 , H01L29/1008 , H01L29/6625 , H01L29/66265 , H01L29/7317 , H01L29/735 , H01L29/785
摘要： A method for fabricating a bipolar transistor device. The method includes the steps of: providing a SOI substrate having a silicon layer thereon; patterning lithographically a fin hardmask on the silicon layer; placing a dummy contact line over a central portion of patterned fin hardmask; doping the collector/emitter regions; depositing a filler layer over the collector region and the emitter region; removing the dummy contact line to reveal a trench and the central portion of the patterned fin hardmask; forming fin-shaped base regions by removing, within the trench, a portion of the silicon layer not covered by the central portion of the patterned fin hardmask after the step of removing the dummy contact line; doping the fin-shaped base region; and forming a contact line by filling the trench with a contact line material over the fin-shaped base regions, where the collector/emitter regions are self-aligned with the contact line.

3. 发明授权

US08637371B2 Non-planar MOSFET structures with asymmetric recessed source drains and methods for making the same 有权
标题翻译：具有非对称凹陷源漏极的非平面MOSFET结构及其制造方法
公开(公告)号：US08637371B2
公开(公告)日：2014-01-28
申请号：US13398339
申请日：2012-02-16
申请人： Josephine B Chang , Paul Chang , Michael A Guillorn , Chung-hsun Lin , Jeffrey W Sleight
发明人： Josephine B Chang , Paul Chang , Michael A Guillorn , Chung-hsun Lin , Jeffrey W Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/0657 , H01L29/66795
摘要： Non-planar Metal Oxide Field Effect Transistors (MOSFETs) and methods for making non-planar MOSFETs with asymmetric, recessed source and drains having improved extrinsic resistance and fringing capacitance. The methods include a fin-last, replacement gate process to form the non-planar MOSFETs and employ a retrograde metal lift-off process to form the asymmetric source/drain recesses. The lift-off process creates one recess which is off-set from a gate structure while a second recess is aligned with the structure. Thus, source/drain asymmetry is achieved by the physical structure of the source/drains, and not merely by ion implantation. The resulting non-planar device has a first channel of a fin contacting a substantially undoped area on the drain side and a doped area on the source side, thus the first channel is asymmetric. A channel on atop surface of a fin is symmetric because it contacts doped areas on both the drain and source sides.
摘要翻译：非平面金属氧化物场效应晶体管（MOSFET）和用于制造具有改进的外在电阻和边缘电容的具有不对称，凹陷源极和漏极的非平面MOSFET的方法。这些方法包括最后一个替代栅极工艺，以形成非平面MOSFET并且采用逆向金属剥离工艺来形成不对称的源极/漏极凹槽。剥离过程产生一个从门结构偏离的凹槽，而第二凹槽与结构对准。因此，源/漏不对称性通过源极/漏极的物理结构实现，而不仅仅是通过离子注入来实现。所得到的非平面器件具有接触漏极侧的基本上未掺杂的区域和源极侧的掺杂区域的翅片的第一通道，因此第一通道是不对称的。鳍的顶表面上的通道是对称的，因为它接触漏极和源极侧上的掺杂区域。

4. 发明授权

US08816328B2 Patterning contacts in carbon nanotube devices 有权
标题翻译：碳纳米管器件中的图案接触
公开(公告)号：US08816328B2
公开(公告)日：2014-08-26
申请号：US13617943
申请日：2012-09-14
申请人： Josephine B Chang , Martin Glodde , Michael A. Guillorn
发明人： Josephine B Chang , Martin Glodde , Michael A. Guillorn
IPC分类号： H01L29/06 , H01L31/00 , H01L29/76 , H01L21/02 , H01L21/84 , H01L21/336 , H01L51/00 , H01L29/775 , H01L29/423
CPC分类号： H01L51/0048 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L51/055 , H01L51/102 , Y10S977/742 , Y10S977/938
摘要： A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT.
摘要翻译：制造基于碳纳米管（CNT）的晶体管的方法包括：提供具有设置在表面上的CNT的衬底; 在所述CNT上形成保护电绝缘层，并在所述保护电绝缘层上形成第一多层抗蚀剂叠层（MLRS）。第一MLRS包括底层，中间层和顶层抗蚀剂。该方法还包括图案化并选择性地移除第一MLRS的一部分以在离开底层的同时限定栅极堆叠的开口; 选择性地去除所述开口内的所述保护电绝缘层的一部分以暴露所述CNT的第一部分; 在开口内和在碳纳米管的暴露的第一部分之后形成栅极堆叠，随后根据本发明的方法形成源极和漏极接触，以暴露CNT的第二和第三部分。

5. 发明授权

US08803129B2 Patterning contacts in carbon nanotube devices 有权
标题翻译：碳纳米管器件中的图案接触
公开(公告)号：US08803129B2
公开(公告)日：2014-08-12
申请号：US13270648
申请日：2011-10-11
申请人： Josephine B Chang , Martin Glodde , Michael A. Guillorn
发明人： Josephine B Chang , Martin Glodde , Michael A. Guillorn
IPC分类号： H01L29/06 , H01L31/00 , H01L29/76 , H01L21/02 , H01L21/84 , H01L21/336 , H01L51/00 , H01L29/775 , H01L29/423
CPC分类号： H01L51/0048 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L51/055 , H01L51/102 , Y10S977/742 , Y10S977/938
摘要： A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.
摘要翻译：结构包括具有设置在表面上的碳纳米管（CNT）的基板。 CNT部分地设置在保护性电绝缘层内。该结构还包括设置在衬底上的栅极堆叠。未被保护电绝缘层覆盖的CNT的长度的第一部分通过栅极堆叠。源极和漏极触点设置成与栅极堆叠相邻，其中未被保护电绝缘层覆盖的CNT的长度的第二和第三部分导电地电耦合到源极和漏极触点。栅极堆叠以及源极和漏极触点包含在保护电绝缘层内并且设置在保护性电绝缘层之上的电绝缘的有机平坦化层内。还描述了制造CNT基晶体管的方法。

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