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1. 发明授权

US5644470A Autodocking hardware for installing and/or removing adapter cards without opening the computer system cover 失效
标题翻译：自动安装硬件，用于安装和/或卸下适配器卡，而不打开计算机系统盖
公开(公告)号：US5644470A
公开(公告)日：1997-07-01
申请号：US552186
申请日：1995-11-02
申请人： Melvin Kent Benedict , Patrick Allen Buckland , Richard Allen Kelley , Danny Marvin Neal , Price Ward Oman , Carl Raymond Waters
发明人： Melvin Kent Benedict , Patrick Allen Buckland , Richard Allen Kelley , Danny Marvin Neal , Price Ward Oman , Carl Raymond Waters
IPC分类号： G06F1/18 , G06F13/40 , H05K7/14 , G06F1/16 , H01R13/629 , H05K7/10
CPC分类号： G06F1/185 , G06F1/184 , G06F1/186 , G06F13/409 , H05K7/1409
摘要： A computer system is provided which allows a user to remove or install feature cards without removing the cover to entire computer. A computer cover is provided with rectangular openings which correspond in alignment and size to an electrical connector on the system board. The feature card can then be mechanically attached to the computer cover, or a frame member, with a pivot and guide member. A handle is provided which will allow the user to apply pressure to the card, via the guide member in order to insert or remove the feature card from the connector on the system board. The guide member is constructed such that a vertical force is applied between the card and connector to ensure proper alignment when inserting and removing the adapter card.
摘要翻译：提供了一种计算机系统，其允许用户移除或安装功能卡，而不将盖覆盖到整个计算机。计算机盖设有矩形开口，其对齐和尺寸对准系统板上的电连接器。特征卡然后可以用枢轴和引导构件机械地附接到计算机盖或框架构件。提供了一种手柄，其允许用户通过引导构件向卡施加压力，以便从系统板上的连接器插入或移除特征卡。引导构件构造成使得在卡和连接器之间施加垂直力以确保插入和移除适配器卡时的正确对准。

2. 发明授权

US5875310A Secondary I/O bus with expanded slot capacity and hot plugging capability 失效
标题翻译：具有扩展槽容量和热插拔能力的二次I / O总线
公开(公告)号：US5875310A
公开(公告)日：1999-02-23
申请号：US653040
申请日：1996-05-24
申请人： Patrick Allen Buckland , Richard Allen Kelley , Danny Marvin Neal
发明人： Patrick Allen Buckland , Richard Allen Kelley , Danny Marvin Neal
IPC分类号： G06F1/26 , G06F13/36 , G06F13/40
CPC分类号： G06F13/4081 , Y02B60/1228 , Y02B60/1235
摘要： A computer system is provided which supports an increase in the number of pluggable cards on the secondary I/O bus by using driver/receiver modules and direction control logic in place of more complex and more expensive bus to bus bridges. The number of pluggable cards on the I/O bus in a computer system is limited by the electrical loading of each card and the frequency of operations on the bus. Reducing the bus frequency provides more signal propagation time. The added signal propagation time supports the extension of the bus by driver/receiver modules and logic which controls the direction the driver/receiver modules drive the bus signals. Further, the driver/receiver modules support changing the hardware configuration of the system by adding or removing an I/O card without the need to cease data processing activity for the entire computer.
摘要翻译：提供了一种计算机系统，其通过使用驱动器/接收器模块和方向控制逻辑来代替更复杂和更昂贵的总线到总线桥，支持次级I / O总线上的可插拔卡的数量的增加。计算机系统中I / O总线上的可插拔卡的数量受到每个卡的电气负载和总线上的操作频率的限制。减少总线频率提供更多的信号传播时间。增加的信号传播时间支持由驱动器/接收器模块和控制驱动器/接收器模块驱动总线信号的方向的逻辑扩展总线。此外，驱动程序/接收器模块支持通过添加或删除I / O卡来更改系统的硬件配置，而无需停止整个计算机的数据处理活动。

3. 发明授权

US5815647A Error recovery by isolation of peripheral components in a data processing system 失效
标题翻译：通过隔离数据处理系统中的外围组件来恢复错误
公开(公告)号：US5815647A
公开(公告)日：1998-09-29
申请号：US862579
申请日：1997-05-23
申请人： Patrick Allen Buckland , Danny Marvin Neal , Steven Mark Thurber
发明人： Patrick Allen Buckland , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1/24 , G06F11/07 , G06F11/20 , G06F11/32 , G06F13/00 , G06F13/40 , G06F11/00
CPC分类号： G06F11/0745 , G06F11/0793 , G06F11/20 , G06F13/4027 , G06F11/326
摘要： The present invention provides a computer system which allows a user to identify which one of a plurality of feature cards has issued an error signal. The device issuing the error signal is then isolated and error recovery techniques, (or re-initialization) are implemented only on the device with the error condition. The computer system includes additional control logic, along with a bridge chip that interconnects different information buses and at least one connector slot for receiving a feature card, which implements specific functions such as I/O, memory, or the like. When it is determined that an error signal is present the system hardware activates and holds a reset signal to the device which issued the error signal. Additionally, a status bit in a register in the bridge chip is set. The device driver corresponding to the device that issued the error signal then reads the status bit and verifies that an error has occurred and then resets the bridge and resets, or initializes only the device having the error condition.
摘要翻译：本发明提供一种计算机系统，其允许用户识别多个特征卡中的哪一个已经发出错误信号。然后发出错误信号的设备被隔离，并且仅在具有错误条件的设备上实现错误恢复技术（或重新初始化）。计算机系统包括附加控制逻辑，以及互连不同信息总线的桥接芯片和用于接收特征卡的至少一个连接器插槽，其实现诸如I / O，存储器等的特定功能。当确定存在错误信号时，系统硬件激活并保持复位信号到发出错误信号的装置。此外，桥接芯片中的寄存器中的状态位被置位。对应于发出错误信号的设备的设备驱动程序读取状态位并验证是否发生错误，然后复位桥接器并复位，或仅初始化具有错误条件的设备。

4. 发明授权

US06493779B1 Method and system for interrupt handling using device pipelined packet transfers 失效
标题翻译：使用设备流水线分组传输的中断处理方法和系统
公开(公告)号：US06493779B1
公开(公告)日：2002-12-10
申请号：US09224111
申请日：1998-12-21
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译：提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。

5. 发明授权

US06418497B1 Method and system for interrupt handling using system pipelined packet transfers 失效
标题翻译：使用系统流水线分组传输的中断处理方法和系统
公开(公告)号：US06418497B1
公开(公告)日：2002-07-09
申请号：US09224119
申请日：1998-12-21
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F948
CPC分类号： G06F13/26
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译：提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。

6. 发明授权

US06182178B2 Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across a PCI host bridge supporting multiple PCI buses 失效
标题翻译：支持通过支持多个PCI总线的PCI主机桥的外围组件互连（PCI）对等访问的方法和系统
公开(公告)号：US06182178B2
公开(公告)日：2001-01-30
申请号：US09106953
申请日：1998-06-30
申请人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1338
CPC分类号： G06F13/4045
摘要： A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. First and second PCI local buses are connected to the system bus through a PCI host bridge. The first and second PCI local buses have sets of in-line electronic switches, dividing the PCI local buses into PCI local bus segments supporting a plurality of PCI peripheral component slots for connecting PCI devices. The sets of in-line electronic switches are open and closed in accordance with bus control logic within the PCI host bridge allowing up to fourteen or more PCI peripheral component slots for connecting up to fourteen PCI devices to have access through a single PCI host bridge to the system bus. An internal PCI-to-PCI bridge is provided to allow a PCI device to share data with another PCI device as peer-to-peer devices across the first and second PCI local bus segments.
摘要翻译：公开了一种通过在数据处理系统内具有多个PCI接口的单个PCI主机桥来支持多个外围组件互连（PCI）局部总线的方法和系统。根据本发明的方法和系统，处理器和系统存储器连接到系统总线。第一和第二PCI本地总线通过PCI主机桥连接到系统总线。第一和第二PCI本地总线具有一组在线电子开关，将PCI本地总线划分成支持用于连接PCI设备的多个PCI外围组件插槽的PCI本地总线段。根据PCI主机桥中的总线控制逻辑，这些在线电子开关是打开和关闭的，允许多达十四个或更多个PCI外设组件插槽，用于连接多达十四个PCI设备，以通过单个PCI主机桥访问系统总线。提供内部PCI至PCI桥接器，以允许PCI设备与第一和第二PCI本地总线段之间的对等设备与另一PCI设备共享数据。

7. 发明授权

US6070211A Driver/receiver circuitry for enhanced PCI bus with differential signaling 失效
标题翻译：驱动器/接收器电路，用于具有差分信号的增强型PCI总线
公开(公告)号：US6070211A
公开(公告)日：2000-05-30
申请号：US872823
申请日：1997-06-11
申请人： Danny Marvin Neal , Charles Bertram Perkins, Jr. , Richard Allen Kelley , Paul Lee Clouser
发明人： Danny Marvin Neal , Charles Bertram Perkins, Jr. , Richard Allen Kelley , Paul Lee Clouser
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4072
摘要： A system of supporting differential signalling circuitry in an enhanced PCI bus within a data processing system is disclosed The enhanced PCI bus comprises a plurality of differential signal conductor pairs. A system and method in accordance with the present invention comprises a system for providing each of the plurality of differential signal pairs over a first line and a second line, the first line having a front end and a back end, the second line having a front end and a back end. The system and method includes a differential driver for driving the first line and the second line with a small voltage change of equal amounts in opposite direction to change logic states, a receiver for sensing a voltage change between the first line and the second line and a termination network coupled to the first line and second line for terminating the first line and the second line. According to the system and method disclosed herein, the present invention provides for higher frequency capability and lower noise to signal ratio, thereby allowing the enhenced PCI bus to be compatible with a legacy PCI bus.
摘要翻译：公开了一种在数据处理系统内的增强型PCI总线中支持差分信令电路的系统。增强型PCI总线包括多个差分信号导体对。根据本发明的系统和方法包括用于在第一线和第二线上提供多个差分信号对中的每一个的系统，第一线具有前端和后端，第二线具有前端结束和后端。该系统和方法包括用于驱动第一线路和第二线路的差分驱动器，其具有相反方向上相等量的小的电压变化以改变逻辑状态，用于感测第一线路和第二线路之间的电压变化的接收机以及耦合到第一线路的终端网络和用于终止第一线路和第二线路的第二线路。根据本文公开的系统和方法，本发明提供了更高的频率能力和更低的噪声与信号比，从而允许增强的PCI总线与传统PCI总线兼容。

8. 发明授权

US06233636B1 Method and system for allowing PCI bus transactions to be performed at higher operating frequencies 失效
标题翻译：允许在较高工作频率下执行PCI总线事务的方法和系统
公开(公告)号：US06233636B1
公开(公告)日：2001-05-15
申请号：US09204919
申请日：1998-12-03
申请人： Richard Allen Kelley , Danny Marvin Neal , Kenneth A. Riek
发明人： Richard Allen Kelley , Danny Marvin Neal , Kenneth A. Riek
IPC分类号： G06F1338
CPC分类号： G06F13/423
摘要： Method and system aspects for enhancing a peripheral component interconnect (PCI) bus to achieve higher frequencies of operation are described. A system aspect includes at least one source synchronous strobe line for providing a source synchronous strobe signal, and at least one PCI compliant device for driving the source synchronous strobe signal to clock data and address on and off a PCI bus, wherein a cycle time for data transactions is reduced. With the present invention, significantly higher frequency capability of PCI is enabled by defining a different clocking signal and protocol for clocking data on and off the bus. A very significant timing budget savings results through the use of a source synchronous strobe for clocking data. Cycle time for bus transactions is therefore reduced, so that the frequency of operation for a synchronous bus is increased. These and other advantages of the aspects of the present invention will be more fully understood in conjunction with the following detailed description and accompanying drawings.
摘要翻译：描述了用于增强外围组件互连（PCI）总线以实现更高频率的操作的方法和系统方面。系统方面包括用于提供源同步选通信号的至少一个源同步选通线，以及用于驱动源同步选通信号以对PCI总线进行时钟数据和地址的至少一个PCI兼容设备，其中，周期时间数据交易减少。利用本发明，通过定义不同的时钟信号和用于在总线上关闭数据时钟的协议来实现PCI的显着更高的频率能力。通过使用源同步选通来计时数据，节省了非常大的时间预算。因此，总线事务的周期时间减少，使得同步总线的操作频率增加。结合以下详细描述和附图，将更全面地理解本发明方面的这些和其它优点。

9. 发明授权

US5838995A System and method for high frequency operation of I/O bus 失效
标题翻译： I / O总线高频运行的系统和方法
公开(公告)号：US5838995A
公开(公告)日：1998-11-17
申请号：US573682
申请日：1995-12-18
申请人： Wen-Tzer Thomas Chen , Richard Allen Kelley , Danny Marvin Neal
发明人： Wen-Tzer Thomas Chen , Richard Allen Kelley , Danny Marvin Neal
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/405
摘要： An extension to an I/O bus and bridge chip is provided which allows higher speed operations. This includes control logic which switches between different data transfer speeds. A host bridge interconnects a system bus with an I/O bus. Included in the host bridge is both a high frequency and low frequency clock. The bridge chip normally operates at the lower frequency and initiates communication with the I/O at this low frequency. If the I/O device is capable of operating at a higher frequency, then a control signal is transmitted from the I/O device to the bridge chip. In response to the receipt of this signal, control logic in the bridge chip causes the higher frequency clock in the bridge chip to be activated such that the host bridge, bus and I/O device are all then operating at the higher frequency.
摘要翻译：提供了对I / O总线和桥接芯片的扩展，允许更高速度的操作。这包括在不同数据传输速度之间切换的控制逻辑。主桥将系统总线与I / O总线互连。主桥包括高频和低频时钟。桥芯片通常以较低频率工作，并在该低频率下启动与I / O的通信。如果I / O设备能够以较高的频率工作，则控制信号从I / O设备发送到桥接芯片。响应于该信号的接收，桥芯片中的控制逻辑导致桥接芯片中的较高频率时钟被激活，使得主桥，总线和I / O设备全部以更高的频率工作。

10. 发明授权

US06425024B1 Buffer management for improved PCI-X or PCI bridge performance 失效
标题翻译：缓冲管理，用于改进PCI-X或PCI桥性能
公开(公告)号：US06425024B1
公开(公告)日：2002-07-23
申请号：US09314044
申请日：1999-05-18
申请人： Richard Allen Kelley , Danny Marvin Neal , Lawrence Dean Whitley , Adalberto Guillermo Yanes
发明人： Richard Allen Kelley , Danny Marvin Neal , Lawrence Dean Whitley , Adalberto Guillermo Yanes
IPC分类号： G06F300
CPC分类号： G06F13/4059
摘要： Buffer management for improved PCI-X or PCI bridge performance. A system and method for managing transactions across a PCI-X or PCI bridge, and a system and method of waiting for, increasing, and/or optimizing the available buffers for transaction size or sizes across a PCI-X or PCI bridge. Transactions are processed across the bridge, and the bridge has buffers with actual available buffer space used for receiving and processing the transactions. Transaction size of the transaction is determined. The system and method sets an available free block which is a set amount of available buffer space that is to be freed up before certain larger size transactions are processed. The system and method waits for the actual available buffer space to free up to and reach the available free block. The certain larger size transactions are then processed when the actual available buffer space has reached the available free block. The processing of the transaction involves accepting the transaction if the transaction size is not greater than the actual available buffer space, retrying the transaction for processing by the bridge when the transaction size is less than the available free block but greater than the actual available buffer space, retrying the transaction by the bridge when the transaction size is greater than the available free block and greater than the available buffer space until the available buffer space is greater than or equal to the available free block, and accepting the transaction and then disconnecting once the actual available buffers are filled or at an end of the transaction.
摘要翻译：缓冲管理，用于改进PCI-X或PCI桥性能。用于管理PCI-X或PCI桥上的事务的系统和方法，以及等待，增加和/或优化可用缓冲区以用于跨PCI-X或PCI桥的事务大小或尺寸的系统和方法。事务在整个桥上进行处理，桥接器具有用于接收和处理事务的实际可用缓冲区空间的缓冲区。确定交易的交易大小。系统和方法设置一个可用的空闲块，它是在处理某些更大规模的事务之前要释放的一定量的可用缓冲区空间。系统和方法等待实际可用的缓冲区空间释放到达可用的空闲块。然后当实际的可用缓冲区空间达到可用的空闲块时，处理某些较大的事务。事务的处理涉及如果事务大小不大于实际可用缓冲区空间，则接受事务，当事务大小小于可用空闲块但大于实际可用缓冲区空间时，重试事务处理桥，当事务大小大于可用空闲块并且大于可用缓冲区空间，直到可用缓冲区空间大于或等于可用可用块，并接受事务然后断开一次实际的可用缓冲区将被填充或在事务结束。

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