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1. 发明授权

US06233636B1 Method and system for allowing PCI bus transactions to be performed at higher operating frequencies 失效
标题翻译：允许在较高工作频率下执行PCI总线事务的方法和系统
公开(公告)号：US06233636B1
公开(公告)日：2001-05-15
申请号：US09204919
申请日：1998-12-03
申请人： Richard Allen Kelley , Danny Marvin Neal , Kenneth A. Riek
发明人： Richard Allen Kelley , Danny Marvin Neal , Kenneth A. Riek
IPC分类号： G06F1338
CPC分类号： G06F13/423
摘要： Method and system aspects for enhancing a peripheral component interconnect (PCI) bus to achieve higher frequencies of operation are described. A system aspect includes at least one source synchronous strobe line for providing a source synchronous strobe signal, and at least one PCI compliant device for driving the source synchronous strobe signal to clock data and address on and off a PCI bus, wherein a cycle time for data transactions is reduced. With the present invention, significantly higher frequency capability of PCI is enabled by defining a different clocking signal and protocol for clocking data on and off the bus. A very significant timing budget savings results through the use of a source synchronous strobe for clocking data. Cycle time for bus transactions is therefore reduced, so that the frequency of operation for a synchronous bus is increased. These and other advantages of the aspects of the present invention will be more fully understood in conjunction with the following detailed description and accompanying drawings.
摘要翻译：描述了用于增强外围组件互连（PCI）总线以实现更高频率的操作的方法和系统方面。系统方面包括用于提供源同步选通信号的至少一个源同步选通线，以及用于驱动源同步选通信号以对PCI总线进行时钟数据和地址的至少一个PCI兼容设备，其中，周期时间数据交易减少。利用本发明，通过定义不同的时钟信号和用于在总线上关闭数据时钟的协议来实现PCI的显着更高的频率能力。通过使用源同步选通来计时数据，节省了非常大的时间预算。因此，总线事务的周期时间减少，使得同步总线的操作频率增加。结合以下详细描述和附图，将更全面地理解本发明方面的这些和其它优点。

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