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1. 发明申请

US20060105507A1 Method to form Si-containing SOI and underlying substrate with different orientations 失效
标题翻译：形成含Si的SOI和具有不同取向的下层衬底的方法
公开(公告)号：US20060105507A1
公开(公告)日：2006-05-18
申请号：US10992150
申请日：2004-11-18
申请人： Meikei Ieong , Devendra Sadana , Ghavam Shahidi
发明人： Meikei Ieong , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/84
CPC分类号： H01L21/76251 , H01L21/2007
摘要： A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.
摘要翻译：一种形成包含上层含Si层和下层含Si层的混合SOI衬底的方法，其中上层含Si层和下层含Si层具有不同的结晶取向。根据本发明，掩埋绝缘区域可以位于一个含硅层内或通过位于两个含Si层之间的界面。

2. 发明申请

US20060275961A1 Strained silicon CMOS on hybrid crystal orientations 有权
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US20060275961A1
公开(公告)日：2006-12-07
申请号：US11492271
申请日：2006-07-25
申请人： Kevin Chan , Meikei Ieong , Alexander Reznicek , Devendra Sadana , Leathen Shi , Min Yang
发明人： Kevin Chan , Meikei Ieong , Alexander Reznicek , Devendra Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/84
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

3. 发明申请

US20060211184A1 Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique 失效
标题翻译：超薄Si沟道MOSFET采用自对准氧注入和镶嵌技术
公开(公告)号：US20060211184A1
公开(公告)日：2006-09-21
申请号：US11436756
申请日：2006-05-18
申请人： Diane Boyd , Bruce Doris , Meikei Ieong , Devendra Sadana
发明人： Diane Boyd , Bruce Doris , Meikei Ieong , Devendra Sadana
IPC分类号： H01L21/84
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78609 , H01L29/78684
摘要： The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located on top of and in contact with said buried insulating layer; and a gate region located atop said SOI layer, wherein said localized oxide region is self-aligned with the gate region. A method for forming the inventive MOSFET is also provided comprising forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.
摘要翻译：本发明提供一种具有低外部电阻的薄沟道MOSFET。广义而言，包括位于掩埋绝缘层顶部的SOI层的绝缘体上硅结构，所述SOI层具有沟槽区，该沟道区被存在位于并接触之下的下面的局部氧化物区域与所述掩埋绝缘层; 以及位于所述SOI层上方的栅极区域，其中所述局部氧化物区域与栅极区域自对准。还提供了一种用于形成本发明的MOSFET的方法，包括在衬底顶部形成虚拟栅极区; 通过所述伪栅极注入形成氧化物的掺杂剂，以在与沟道区域的伪栅极区对准的衬底的一部分中产生局部氧化物区域; 形成邻接所述沟道区的源/漏扩展区; 并用栅极导体代替虚拟栅极。

4. 发明申请

US20050118826A1 Ultra-thin Si MOSFET device structure and method of manufacture 失效
标题翻译：超薄Si MOSFET器件结构及制造方法
公开(公告)号：US20050118826A1
公开(公告)日：2005-06-02
申请号：US10725848
申请日：2003-12-02
申请人： Diane Boyd , Bruce Doris , Meikei Ieong , Devendra Sadana
发明人： Diane Boyd , Bruce Doris , Meikei Ieong , Devendra Sadana
IPC分类号： H01L21/265 , H01L21/28 , H01L21/311 , H01L21/336 , H01L29/10 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28194 , H01L21/26533 , H01L21/28202 , H01L29/1083 , H01L29/49 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/78
摘要： The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.
摘要翻译：本发明包括用于形成超薄沟道MOSFET的方法和由其制造的超薄沟道MOSFET。具体地说，该方法包括：在SOI层的下方提供具有掩埋绝缘层的SOI衬底; 在SOI层顶上形成焊盘堆叠; 通过所述垫堆叠的顶部形成具有通道的块掩模; 在所述掩埋绝缘层的顶部上的所述SOI层中提供局部氧化物区域，从而使所述SOI层的一部分变薄，所述局部氧化物区域与所述沟道通孔自对准; 在通道通道中形成一个门; 至少去除阻挡掩模; 以及在与SOI层的薄化部分邻接的SOI层中形成源极/漏极延伸部。提供局部氧化物区域还包括通过沟道通孔将氧掺杂剂注入到SOI层的一部分中; 并退火掺杂剂以产生局部氧化物区域。

5. 发明申请

US20070228473A1 ULTRA-THIN Si MOSFET DEVICE STRUCTURE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：超薄SiFET器件结构及其制造方法
公开(公告)号：US20070228473A1
公开(公告)日：2007-10-04
申请号：US11758265
申请日：2007-06-05
申请人： Diane Boyd , Bruce Doris , Meikei Ieong , Devendra Sadana
发明人： Diane Boyd , Bruce Doris , Meikei Ieong , Devendra Sadana
IPC分类号： H01L29/786
CPC分类号： H01L21/26533 , H01L21/2658 , H01L21/28194 , H01L21/28202 , H01L29/1083 , H01L29/49 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/78
摘要： The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.
摘要翻译：本发明包括用于形成超薄沟道MOSFET的方法和由其制造的超薄沟道MOSFET。具体地说，该方法包括：在SOI层的下方提供具有掩埋绝缘层的SOI衬底; 在SOI层顶上形成焊盘堆叠; 通过所述垫堆叠的顶部形成具有通道的块掩模; 在所述掩埋绝缘层的顶部上的所述SOI层中提供局部氧化物区域，从而使所述SOI层的一部分变薄，所述局部氧化物区域与所述沟道通孔自对准; 在通道通道中形成一个门; 至少去除阻挡掩模; 以及在与SOI层的薄化部分邻接的SOI层中形成源极/漏极延伸部。提供局部氧化物区域还包括通过沟道通孔将氧掺杂剂注入到SOI层的一部分中; 并退火掺杂剂以产生局部氧化物区域。

6. 发明申请

US20050236687A1 Strained silicon CMOS on hybrid crystal orientations 失效
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US20050236687A1
公开(公告)日：2005-10-27
申请号：US10830347
申请日：2004-04-22
申请人： Kevin Chan , Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Alexander Reznicek , Kern Rim , Devendra Sadana , Leathen Shi , Jeffrey Sleight , Min Yang
发明人： Kevin Chan , Bruce Doris , Kathryn Guarini , Meikei Ieong , Shreesh Narasimha , Alexander Reznicek , Kern Rim , Devendra Sadana , Leathen Shi , Jeffrey Sleight , Min Yang
IPC分类号： H01L27/08 , H01L21/02 , H01L21/20 , H01L21/336 , H01L21/762 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/04 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

7. 发明申请

US20050116289A1 Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique 有权
标题翻译：超薄Si沟道MOSFET采用自对准氧注入和镶嵌技术
公开(公告)号：US20050116289A1
公开(公告)日：2005-06-02
申请号：US10725849
申请日：2003-12-02
申请人： Diane Boyd , Bruce Doris , Meikei Ieong , Devendra Sadana
发明人： Diane Boyd , Bruce Doris , Meikei Ieong , Devendra Sadana
IPC分类号： H01L21/336 , H01L29/786 , H01L27/01
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78609 , H01L29/78684
摘要： The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located on top of and in contact with said buried insulating layer; and a gate region located atop said SOI layer, wherein said localized oxide region is self-aligned with the gate region. A method for forming the inventive MOSFET is also provided comprising forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.
摘要翻译：本发明提供一种具有低外部电阻的薄沟道MOSFET。广义而言，包括位于掩埋绝缘层顶部的SOI层的绝缘体上硅结构，所述SOI层具有沟槽区，该沟道区被存在位于并接触之下的下面的局部氧化物区域而变薄与所述掩埋绝缘层; 以及位于所述SOI层上方的栅极区域，其中所述局部氧化物区域与栅极区域自对准。还提供了一种用于形成本发明的MOSFET的方法，包括在衬底顶部形成虚拟栅极区; 通过所述伪栅极注入形成氧化物的掺杂剂，以在与沟道区域的伪栅极区对准的衬底的一部分中产生局部氧化物区域; 形成邻接所述沟道区的源/漏扩展区; 并用栅极导体代替虚拟栅极。

8. 发明申请

US20080050887A1 METHOD FOR FABRICATING SiGe-ON-INSULATOR (SGOI) AND Ge-ON-INSULATOR (GOI) SUBSTRATES 有权
标题翻译：用于制造SiGe-ON绝缘体（SGOI）和Ge-ON-Insulator（GOI）衬底的方法
公开(公告)号：US20080050887A1
公开(公告)日：2008-02-28
申请号：US11924207
申请日：2007-10-25
申请人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Tze-chiang Chen , Guy Cohen , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L31/02327 , H01L31/028 , H01L31/1812 , Y02E10/547
摘要： A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.
摘要翻译：提供了绝缘体上（锗）绝缘体（GOI）衬底材料的方法，通过该方法生产的GOI衬底材料和至少可以包括本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶部的掩埋绝缘体层，以及位于掩埋绝缘体层顶部的优选纯Ge的Ge含有层。在本发明的GOI基板材料中，Ge含有层也可以称为GOI膜。 GOI膜是可以形成器件的本发明的基底材料的层。

9. 发明申请

US20070164356A1 Strained semiconductor-on-insulator (sSOI) by a simox method 有权
标题翻译：应用绝缘体半导体（sSOI）通过simox方法
公开(公告)号：US20070164356A1
公开(公告)日：2007-07-19
申请号：US11332564
申请日：2006-01-13
申请人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
发明人： Thomas Adam , Stephen Bedell , Joel de Souza , Keith Fogel , Alexander Reznicek , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/76243 , H01L29/66772 , H01L29/7849 , H01L29/78654
摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.
摘要翻译：提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

10. 发明申请

US20060172505A1 Structure and method of integrating compound and elemental semiconductors for high-performace CMOS 失效
标题翻译：化合物和元素半导体用于高性能CMOS的结构和方法
公开(公告)号：US20060172505A1
公开(公告)日：2006-08-03
申请号：US11046912
申请日：2005-01-31
申请人： Steven Koester , Devendra Sadana , Ghavam Shahidi
发明人： Steven Koester , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/823807 , H01L21/02002 , H01L21/76254 , H01L21/76256 , H01L21/8258 , H01L21/84 , H01L27/1203
摘要： A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.
摘要翻译：制造半导体衬底的方法包括在化合物半导体衬底上外延生长元素半导体层。绝缘层沉积在元素半导体层的顶部上，以形成第一衬底。第一衬底被晶片结合到单晶Si衬底上，使得绝缘层与单晶Si衬底结合。半导体器件包括单晶衬底和形成在单晶衬底上的电介质层。在介电层上形成半导体化合物，在半导体化合物附近形成与半导体化合物晶格匹配的元素半导体材料。

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