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1. 发明授权

US6004886A Liquid phase deposition method for forming silicon dioxide film on HGCDTE or other II-VI semiconductor substrate 失效
标题翻译：用于在HGCDTE或其他II-VI半导体衬底上形成二氧化硅膜的液相沉积方法
公开(公告)号：US6004886A
公开(公告)日：1999-12-21
申请号：US960913
申请日：1997-10-30
申请人： Mau-Phon Houng , Yeong-Her Wang , Na-Fu Wang
发明人： Mau-Phon Houng , Yeong-Her Wang , Na-Fu Wang
IPC分类号： H01L21/471 , H01L21/31 , H01L21/469
CPC分类号： H01L21/471
摘要： A method for growing a silicon dioxide film on a HgCdTe substrate includes a first step in which the HgCdTe substrate is cleaned with an alkaline aqueous solution. The cleaned HgCdTe substrate is then dried before being immersed in a liquid phase deposition solution in which the silicon dioxide film is deposited on the surface of the HgCdTe substrate at the rate as high as 1672 .ANG./hr. The silicon dioxide film has a refraction rate as high as 1.465.
摘要翻译：在HgCdTe衬底上生长二氧化硅膜的方法包括第一步骤，其中用碱性水溶液清洗HgCdTe衬底。然后将清洁的HgCdTe基板干燥，然后浸入其中二氧化硅膜以高达1672安格/小时的速率沉积在HgCdTe基板的表面上的液相沉积溶液中。二氧化硅膜的折射率高达1.465。

2. 发明授权

US06689645B2 Method of surface treatment on the improvement of electrical properties for doped silicon oxides (SiO2) films 有权
标题翻译：表面处理改善掺杂氧化硅（SiO2）薄膜电性能的方法
公开(公告)号：US06689645B2
公开(公告)日：2004-02-10
申请号：US09851974
申请日：2001-05-10
申请人： Mau-Phon Houng , Yeong-Her Wang , Wai-Jyh Chang
发明人： Mau-Phon Houng , Yeong-Her Wang , Wai-Jyh Chang
IPC分类号： H01L21335
CPC分类号： H01L21/02052 , H01L21/31629
摘要： In the fabrication of gate oxides in IC process, a suitable cleaning/etching process is required to remove the native oxides and reduce surface microroughness in addition to standard RCA cleaning. For ultrathin oxide thickness (
摘要翻译：在IC工艺中栅极氧化物的制造中，除了标准的RCA清洁之外，还需要适当的清洁/蚀刻工艺去除天然氧化物并降低表面微观粗糙度。对于超薄氧化物厚度（<10nm），具有无自然氧化物和H钝化硅（Si）表面的重要问题是确保高击穿场，高电荷到击穿和低漏电流。根据这些概念，我们提出了一种简单的两步氟化氢（HF）蚀刻工艺的发明，以改善液相沉积氟化硅氧化物（LPD-SiOF）的电性能，包括有效去除天然氧化物，降低界面陷阱密度（〜10 10 eV-1 cm -2），表面微粗糙度（Ra = 0.1nm）的降低和击穿场的提高（〜9.7 MV / cm）。此外，快速热退火（RTA）也用于进一步提高氧化物质量。发现击穿场增加18％，界面陷阱密度降低33％。除了适用于LPD-氧化硅（SiO 2）之外，该技术也适用于其他掺杂氧化物。该技术有助于在未来的ULSI工艺中获得用于超薄栅极氧化物的高质量和低成本的氧化硅。

3. 发明授权

US06326317B1 Method for fabricating metal oxide semiconductor field effect transistor (MOSFET) 有权
标题翻译：制造金属氧化物半导体场效应晶体管（MOSFET）的方法
公开(公告)号：US06326317B1
公开(公告)日：2001-12-04
申请号：US09399680
申请日：1999-09-21
申请人： Hwei-Heng Wang , Yeong-Her Wang , Mau-Phon Houng
发明人： Hwei-Heng Wang , Yeong-Her Wang , Mau-Phon Houng
IPC分类号： H01L2131
CPC分类号： H01L29/66522 , H01L21/02241 , H01L21/02255 , H01L21/28264 , H01L21/30621 , H01L21/31666
摘要： Disclosed is a method for manufacturing a metal oxide semiconductor FET (MOSFET), which utilizes a low-temperature liquid phase oxidation for III-V group. The method includes the steps of (a) providing a substrate, (b) forming an epitaxial layer on the substrate, (c) defining and forming a drain and a source on a portion of the epitaxial layer, (d) forming a recess in an another portion of the epitaxial layer, (e) forming an oxide layer on a surface of the recess by relatively low-temperature oxidation, and (f) forming a gate on a portion of the oxide layer between the drain and source. In addition, the method further includes two selective procedures, that is, a synchronic sulfurated passivation process which can be performed with the growth of the oxide film simultaneously, and a rapid thermal annealing (RTA) process.
摘要翻译：公开了一种利用III-V族低温液相氧化的金属氧化物半导体FET（MOSFET）的制造方法。该方法包括以下步骤：（a）提供衬底，（b）在衬底上形成外延层，（c）在外延层的一部分上界定并形成漏极和源极;（d）所述外延层的另一部分，（e）通过相对低温氧化在所述凹部的表面上形成氧化物层，以及（f）在所述漏极和源极之间的所述氧化物层的一部分上形成栅极。此外，该方法还包括两个选择性程序，即可以同时进行氧化膜生长的同步硫化钝化工艺，以及快速热退火（RTA）工艺。

4. 发明授权

US5998304A Liquid phase deposition method for growing silicon dioxide film on III-V semiconductor substrate treated with ammonium hydroxide 失效
标题翻译：在用氢氧化铵处理的III-V半导体衬底上生长二氧化硅膜的液相沉积方法
公开(公告)号：US5998304A
公开(公告)日：1999-12-07
申请号：US922186
申请日：1997-09-02
申请人： Mau-Phon Houng , Yeong-Her Wang , Chien-Jung Huang
发明人： Mau-Phon Houng , Yeong-Her Wang , Chien-Jung Huang
IPC分类号： H01L21/316 , H01L21/8252
CPC分类号： H01L21/316 , Y10S438/905 , Y10S438/906 , Y10S438/93 , Y10S438/933
摘要： A liquid phase deposition method involves the use of a supersaturated hydrofluosilicic acid aqueous solution for growing a silicon dioxide film at low temperature (30.degree. C.-50.degree. C.) on a III-V semiconductor, such as a gallium arsenide substrate. The silicon dioxide film may be used in a bipolar transistor or as a field oxide of MOS (metal oxide semiconductor). The III-V semiconductor substrate is chemically treated with an alkaline aqueous solution such as ammonium hydroxide so that the surface of the III-V semiconductor substrate is modified to facilitate the growth of the silicon dioxide film by liquid phase deposition. The growth rate of the silicon dioxide film is as fast as 1265 .ANG./hr. The silicon dioxide film has a refractive index ranging between 1.372 and 1.41.
摘要翻译：液相沉积方法涉及使用过饱和的氢氟硅酸水溶液，用于在III-V半导体如砷化镓衬底上在低温（30℃-50℃）下生长二氧化硅膜。二氧化硅膜可以用在双极晶体管中或作为MOS（金属氧化物半导体）的场氧化物。 III-V族半导体衬底用碱性水溶液如氢氧化铵进行化学处理，使得III-V族半导体衬底的表面被改性，以利于通过液相沉积生长二氧化硅膜。二氧化硅膜的生长速度与1265安培/小时一样快。二氧化硅膜的折射率在1.372和1.41之间。

5. 发明授权

US5958519A Method for forming oxide film on III-V substrate 失效
标题翻译：在III-V衬底上形成氧化膜的方法
公开(公告)号：US5958519A
公开(公告)日：1999-09-28
申请号：US929639
申请日：1997-09-15
申请人： Hwei-Heng Wang , Yeong-Her Wang , Mau-Phon Houng
发明人： Hwei-Heng Wang , Yeong-Her Wang , Mau-Phon Houng
IPC分类号： H01L21/316 , B05D1/18
CPC分类号： H01L21/31654
摘要： A method is provided for forming an oxide film on a III-V substrate. The method includes steps of (a) preparing an acidic solution containing a IIIA-ion, (b) adding an basic solution into the acidic solution to provide a growth solution of a specific pH value, and (c) placing the III-V substrate into the growth solution to form the oxide film on the III-V substrate.
摘要翻译：提供了在III-V基板上形成氧化膜的方法。该方法包括以下步骤：（a）制备含有IIIA离子的酸性溶液，（b）将碱性溶液加入到酸性溶液中以提供特定pH值的生长溶液，和（c）将III-V底物进入生长溶液以在III-V底物上形成氧化膜。

6. 发明授权

US07316065B2 Method for fabricating a plurality of elastic probes in a row 有权
标题翻译：一排制造多个弹性探针的方法
公开(公告)号：US07316065B2
公开(公告)日：2008-01-08
申请号：US11364330
申请日：2006-03-01
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
IPC分类号： G01R3/00
CPC分类号： G01R3/00 , G01R1/06716 , G01R1/06744 , G01R1/07342 , H01R13/2414 , H01R43/007 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.
摘要翻译：公开了一排形成多个弹性探针的方法。首先，提供基板，然后在基板上形成成形层，以便平行地提供两个平坦表面。在基板上和形成层上形成光致抗蚀剂层。然后，对光致抗蚀剂层进行图案化以形成与两个平坦表面之间的界面交叉的多个槽，其中在槽中形成有多个弹性探针。在一个实施例中，界面是成形层的边缘斜率，使得每个弹性探针具有至少一个弹性弯曲部分。在芯片探测期间，由于过驱动导致的弹性探针的移动方向垂直于接合焊盘的布置方向，使得弹性探头适用于探测具有高密度和细间距接合焊盘的芯片。

7. 发明申请

US20070152689A1 Modular probe card 有权
标题翻译：模块式探针卡
公开(公告)号：US20070152689A1
公开(公告)日：2007-07-05
申请号：US11322408
申请日：2006-01-03
申请人： Yi-Chang Lee , An-Hong Liu , Hsiang-Ming Huang , Yao-Jung Lee , Yeong-Her Wang
发明人： Yi-Chang Lee , An-Hong Liu , Hsiang-Ming Huang , Yao-Jung Lee , Yeong-Her Wang
IPC分类号： G01R31/02
CPC分类号： G01R1/07378
摘要： A modular probe card comprises a printed circuit board, an interposer, and a probe head where the printed circuit board has a plurality of first contact pads, the probe head has a plurality of second contact pads. The interposer is disposed between the printed circuit board and the probe head where the interposer includes a substrate and a plurality of pogo pins. The substrate has a first surface, a second surface, and a plurality of through holes penetrating from the first surface to the second surface. The pogo pins are secured in the through holes of the substrate. Each of the pogo pins has a first contact point, a second contact point, and a spring therebetween, whereby the first contact points are elastically extruded from the first surface to contact the first contact pad, and the second contact points are elastically extruded from the second surface to contact the second contact pad, so as to overcome the poor electrical connections between the printed circuit board and the probe head through the interposer due to poor coplanarity of the first contact pads of the printed circuit board.
摘要翻译：模块化探针卡包括印刷电路板，插入件和探针头，其中印刷电路板具有多个第一接触焊盘，探头具有多个第二接触焊盘。插入器设置在印刷电路板和探针头之间，其中插入器包括基板和多个弹簧销。基板具有从第一表面到第二表面的第一表面，第二表面和多个通孔。弹簧销固定在基板的通孔中。每个弹簧销具有第一接触点，第二接触点和它们之间的弹簧，由此第一接触点从第一表面弹性挤出以接触第一接触垫，并且第二接触点从第二表面接触第二接触焊盘，以便克服印刷电路板和探针头之间通过插入器的不良电连接，因为印刷电路板的第一接触焊盘的共面性差。

8. 发明申请

US20060091510A1 Probe card interposer 审中-公开
标题翻译：探头卡插件
公开(公告)号：US20060091510A1
公开(公告)日：2006-05-04
申请号：US11076935
申请日：2005-03-11
申请人： An-Hong Liu , Yeong-Her Wang , Yao-Jung Lee
发明人： An-Hong Liu , Yeong-Her Wang , Yao-Jung Lee
IPC分类号： H01L23/02
CPC分类号： G01R31/2889 , G01R1/0416 , H05K3/326 , H05K3/4092 , H05K2201/0397 , H05K2201/09909 , H05K2201/10378
摘要： A probe card interposer includes a substrate with a plurality of conductive bumps disposed on first surface of the substrate. Each conductive bump comprises a dielectric core and a plurality of conductive leads. The suspended ends of the conductive wires extend toward the centers of the corresponding dielectric cores and are elastically supported by the corresponding dielectric cores. Therefore, the interposer can be installed between a probe head and a multi-layer PCB to make good electrical contacts to the probe head through the conductive bumps. In the embodiment, a plurality of symmetric conductive bumps are disposed on second surface of the substrate and are electrically connected to the conductive bumps on first surface of the substrate through vias or conductive posts. The conductive bumps can electrically contact the multi-layer PCB.
摘要翻译：探针卡插入件包括具有设置在基板的第一表面上的多个导电凸块的基板。每个导电凸块包括介质芯和多个导电引线。导线的悬挂端部朝向相应介质芯的中心延伸，并被相应的介质芯片弹性地支撑。因此，插入器可以安装在探针头和多层PCB之间，以通过导电凸块与探头头形成良好的电接触。在本实施例中，多个对称导电凸块设置在基板的第二表面上，并且通过通孔或导电柱与基板的第一表面上的导电凸块电连接。导电凸块可以电接触多层PCB。

9. 发明授权

US06853205B1 Probe card assembly 有权
标题翻译：探头卡组合
公开(公告)号：US06853205B1
公开(公告)日：2005-02-08
申请号：US10620448
申请日：2003-07-17
申请人： Shih-Jye Cheng , An-Hong Liu , Yeong-Her Wang , Yuan-Ping Tseng , Yao-Jung Lee
发明人： Shih-Jye Cheng , An-Hong Liu , Yeong-Her Wang , Yuan-Ping Tseng , Yao-Jung Lee
IPC分类号： G01R1/073 , G01R1/18 , G01R31/28 , G01R31/02
CPC分类号： G01R1/07342 , G01R1/06733 , G01R1/18 , G01R31/2889
摘要： A probe card assembly is disclosed. The probe card assembly comprises a stiffener ring combining respectively with an upper printed circuit board and a lower printed circuit board. A plurality of coaxial transmitters are installed in the stiffener ring, and connect to the upper and lower printed circuit boards by cable connectors. The lower printed circuit board is assembled with a detachable probe head which comprises a silicon substrate with probing points and a probe head carrier. A downset is formed at the center of the probe head carrier. The standardized coaxial transmitters, printed circuit boards and probe heads are then assembled as a probe card assembly for testing all sorts of IC products.
摘要翻译：公开了一种探针卡组件。探针卡组件包括分别与上印刷电路板和下印刷电路板组合的加强环。多个同轴发射器安装在加强环中，并通过电缆连接器连接到上下印刷电路板。下部印刷电路板组装有可拆卸的探针头，该探头包括具有探测点的硅衬底和探针头托架。在探针头托架的中心处形成一个凹陷。然后将标准化的同轴发射器，印刷电路板和探头组装成用于测试各种IC产品的探针卡组件。

10. 发明授权

US07477065B2 Method for fabricating a plurality of elastic probes in a row 有权
标题翻译：一排制造多个弹性探针的方法
公开(公告)号：US07477065B2
公开(公告)日：2009-01-13
申请号：US11605443
申请日：2006-11-29
申请人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
发明人： Yi-Chang Lee , An-Hong Liu , Yeong-Her Wang , Yeong-Ching Chao , Hsiang-Ming Huang
IPC分类号： G01R31/02
CPC分类号： G01R3/00 , G01R1/06716 , G01R1/06744 , G01R1/07342 , H01R13/2414 , H01R43/007 , Y10T29/49147 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222
摘要： A method of forming a plurality of elastic probes in a row is disclosed. Firstly, a substrate is provided, then, a shaping layer is formed on the substrate so as to offer two flat surfaces in parallel. A photoresist layer is formed on the substrate and on the shaping layer. Then, the photoresist layer is patterned to form a plurality of slots crossing an interface between the two flat surfaces where a plurality of elastic probes are formed in the slots. In one embodiment, the interface is an edge slope of the shaping layer so that each of the elastic probes has at least an elastic bending portion. During chip probing, the shifting direction of the elastic probes due to overdrives is perpendicular to the arranging direction of the bonding pads so that the elastic probes are suitable for probing chips with high-density and fine-pitch bonding pads.
摘要翻译：公开了一排形成多个弹性探针的方法。首先，提供基板，然后在基板上形成成形层，以便平行地提供两个平坦表面。在基板上和形成层上形成光致抗蚀剂层。然后，对光致抗蚀剂层进行图案化以形成与两个平坦表面之间的界面交叉的多个槽，其中在槽中形成有多个弹性探针。在一个实施例中，界面是成形层的边缘斜率，使得每个弹性探针具有至少一个弹性弯曲部分。在芯片探测期间，由于过驱动导致的弹性探针的移动方向垂直于接合焊盘的布置方向，使得弹性探头适用于探测具有高密度和细间距接合焊盘的芯片。

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