会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Field emission display and method of manufacture
    • 场发射显示及制造方法
    • US06716078B1
    • 2004-04-06
    • US09626979
    • 2000-07-27
    • Matthew StainerShawn M. O'RourkeKazuo KatoSusumu Sakamoto
    • Matthew StainerShawn M. O'RourkeKazuo KatoSusumu Sakamoto
    • H01J9227
    • H01J9/2271H01J29/085
    • A field emission display (30) having an anode plate (10) that has phosphor channels (13, 14, 15). The phosphor channels (13, 14, 15) are formed by depositing a first layer of photosensitive film (58) on a substrate (11). Stripes are patterned into the first layer photosensitive film (58) using ultraviolet light. A second layer of photosensitive film (59) is formed on the first layer of photosensitive film (58). Stripes are patterned into the second layer of photosensitive film (59) using ultraviolet light. The stripes in the second layer of photosensitive film (58) are substantially perpendicular to the first layer of photosensitive film (59). Both layers of photosensitive film are developed to form channel structures. Phosphor is formed in the channel structures to form the phosphor channels (13, 14, 15). The anode plate (10) is coupled to a cathode plate (31) to form the field emission display (30).
    • 具有具有荧光体通道(13,14,15)的阳极板(10)的场致发射显示器(30)。 荧光体通道(13,14,15)通过在基板(11)上沉积第一层感光膜(58)而形成。 使用紫外线将条纹图案化成第一层感光膜(58)。 在第一感光膜(58)上形成第二层感光膜(59)。 使用紫外光将条纹图案化成第二层感光膜(59)。 感光膜(58)的第二层中的条纹基本上垂直于第一层感光膜(59)。 开发两层感光膜以形成通道结构。 在沟道结构中形成荧光体以形成荧光体通道(13,14,15)。 阳极板(10)连接到阴极板(31)以形成场致发射显示器(30)。
    • 7. 发明申请
    • Stepping motor control circuit and analog electronic watch
    • 步进电机控制电路和模拟电子手表
    • US20100238767A1
    • 2010-09-23
    • US12661359
    • 2010-03-16
    • Keishi HonmuraSaburo ManakaKosuke YamamotoAkira TakakuraKenji OgasawaraKazumi SakumotoKazuo KatoTakanori Hasegawa
    • Keishi HonmuraSaburo ManakaKosuke YamamotoAkira TakakuraKenji OgasawaraKazumi SakumotoKazuo KatoTakanori Hasegawa
    • G04B19/04H02P8/38
    • G04C3/143H02P8/02
    • A stepping motor control circuit includes a rotation detecting means which detects an induced signal generated by rotation of a rotor of a stepping motor, and detects a rotation state of the stepping motor according to whether the induced signal exceeds a predetermined reference threshold voltage in a predetermined detection section, and a control means which controls driving of the stepping motor by using any one of a plurality of main driving pulses having energies different from each other or a correction driving pulse with energy higher than energy of each main driving pulse according to a detection result of the rotation detecting means. The detection section is divided into a first section immediately after driving by the main driving pulse, a second section after the first section and a third section after the second section. During the driving of the stepping motor by the main driving pulse, when the rotation detecting means has detected an induced signal exceeding a first reference threshold voltage in the first section and the second section, if an induced signal exceeding a second reference threshold voltage lower than the first reference threshold voltage is not detected in the third section, the control means drives the stepping motor by using the correction driving pulse.
    • 步进电动机控制电路包括旋转检测装置,其检测由步进电动机的转子旋转产生的感应信号,并且根据感应信号是否超过预定的参考阈值电压来检测步进电动机的旋转状态 检测部分和控制装置,其通过使用具有彼此不同的能量的多个主驱动脉冲中的任何一个来控制步进电机的驱动,或者根据检测来控制具有高于每个主驱动脉冲的能量的能量的校正驱动脉冲 旋转检测装置的结果。 检测部分通过主驱动脉冲被分成紧接在驱动之后的第一部分,第一部分之后的第二部分和第二部分之后的第三部分。 在通过主驱动脉冲驱动步进电机的过程中,当旋转检测装置在第一部分和第二部分检测到超过第一参考阈值电压的感应信号时,如果超过第二参考阈值电压的感应信号低于 在第三部分中没有检测到第一参考阈值电压,控制装置通过使用校正驱动脉冲来驱动步进电机。
    • 9. 发明申请
    • Semiconductor integrated circuit having test function and manufacturing method
    • 具有测试功能和制造方法的半导体集成电路
    • US20060184848A1
    • 2006-08-17
    • US11335606
    • 2006-01-20
    • Mitsuo SerizawaKaname YamasakiMasafumi YamamotoKazuo Kato
    • Mitsuo SerizawaKaname YamasakiMasafumi YamamotoKazuo Kato
    • G01R31/28
    • G11C29/4401G01R31/318569G11C29/44G11C29/848G11C2029/0401G11C2029/0405G11C2029/3202
    • The logic integrated circuit comprises a logic circuit having the predetermined logic functions, a read/write memory circuit, a test circuit for testing whether fail bit is included in the memory circuit or not, and a boundary latch circuit formed of a plurality of flip-flop circuits which are capable of latching signals between said logic circuit and said memory circuit and also forming a shift register. Moreover, the logic integrated circuit is further provided with a fail relief information generating circuit for storing test result to the boundary latch circuit during execution of the test with the test circuit and generating the fail relief information for relieving fail of said memory circuit based on the stored test result. The test circuit mounted on the logic integrated circuit can generate the information for relieving fail bit in parallel with the test of a built-in memory circuit and can also output the same information to external side and relieve the RAM within a chip.
    • 逻辑集成电路包括具有预定逻辑功能的逻辑电路,读/写存储器电路,用于测试故障位是否包含在存储器电路中的测试电路,以及由多个触发器组成的边界锁存电路, 触发电路,其能够在所述逻辑电路和所述存储器电路之间锁存信号,并且还形成移位寄存器。 此外,逻辑集成电路还设置有故障补救信息生成电路,用于在与测试电路执行测试期间将测试结果存储到边界锁存电路,并且基于该测试电路产生用于缓解所述存储器电路的故障的故障排除信息 存储测试结果。 安装在逻辑集成电路上的测试电路可以生成与内置存储器电路的测试并行的解除故障位的信息,并且还可以向外部输出相同的信息并释放芯片内的RAM。