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1. 发明授权

US06700163B2 Selective silicide blocking 有权
标题翻译：选择性硅化物封闭
公开(公告)号：US06700163B2
公开(公告)日：2004-03-02
申请号：US09683278
申请日：2001-12-07
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
IPC分类号： H01L2976
CPC分类号： H01L21/823871 , H01L21/823842
摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.
摘要翻译：本文公开了选择性硅化半导体结构及其制造方法。半导体结构在N +扩散或N +有源区域之间的多晶硅线路上存在自杀，并且在多晶硅线路的N + / P +结处的P +扩散或有源区域存在自杀，并且在N +有源区域和P +活性区域上不存在硅化物区。这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

2. 发明授权

US06881672B2 Selective silicide blocking 失效
标题翻译：选择性硅化物封闭
公开(公告)号：US06881672B2
公开(公告)日：2005-04-19
申请号：US10723700
申请日：2003-11-26
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/823871 , H01L21/823842
摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has silicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.
摘要翻译：本文公开了选择性硅化半导体结构及其制造方法。半导体结构在多晶硅线路上存在硅化物，N +扩散区域或N +有源区域与多晶硅线路的N + / P +结处的P +扩散区域或有源区域之间存在硅化物，而N +有源区域和P +活性区域上不存在硅化物区。这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

3. 发明授权

US06778449B2 Method and design for measuring SRAM array leakage macro (ALM) 失效
标题翻译： SRAM阵列泄漏宏（ALM）测量方法与设计
公开(公告)号：US06778449B2
公开(公告)日：2004-08-17
申请号：US10064302
申请日：2002-07-01
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Randy W. Mann , Jeffrey H. Oppold
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Randy W. Mann , Jeffrey H. Oppold
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5006
摘要： A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.
摘要翻译：用于具有通过导线连接在一起的单元阵列的测试结构的方法和结构。导线将电池连接在一起，就像它们是单个电池一样。导线可以包括通用字线; 一个普通的位线公共位线补码线，公共N阱电压线，公共内部地线，公共内部电压线和/或公共接地线。

4. 发明授权

US07190007B2 Isolated fully depleted silicon-on-insulator regions by selective etch 失效
标题翻译：通过选择性蚀刻隔离完全耗尽的绝缘体上硅区域
公开(公告)号：US07190007B2
公开(公告)日：2007-03-13
申请号：US10710821
申请日：2004-08-05
申请人： Matthew J. Breitwisch , Chung H. Lam , Randy W. Mann , Dale W. Martin
发明人： Matthew J. Breitwisch , Chung H. Lam , Randy W. Mann , Dale W. Martin
IPC分类号： H01L29/47
CPC分类号： H01L21/764 , H01L21/76283 , H01L21/76289 , H01L29/78654
摘要： The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 Å.
摘要翻译：本发明提供一种形成超薄且均匀的Si层的方法，包括以下步骤：提供具有由绝缘区分隔开的半导体区域的衬底; 将掺杂剂注入衬底中以在半导体区域的上部含Si表面下方的半导体区域中提供蚀刻差分掺杂部分; 在包括半导体区域和绝缘区域的衬底中形成沟槽; 从所述半导体区域去除所述蚀刻差分掺杂部分以在所述半导体区域的上表面下方形成空腔; 以及用沟槽电介质填充所述沟槽，其中所述沟槽电介质材料包围在所述半导体区域的所述上部含Si表面之下的空腔。半导体区域的上部含Si表面具有小于约的均匀厚度。

5. 发明授权

US08987700B2 Thermally confined electrode for programmable resistance memory 有权
标题翻译：用于可编程电阻存储器的热电极
公开(公告)号：US08987700B2
公开(公告)日：2015-03-24
申请号：US13310583
申请日：2011-12-02
申请人： Sheng-Chih Lai , Hsiang-Lan Lung , Matthew J. Breitwisch
发明人： Sheng-Chih Lai , Hsiang-Lan Lung , Matthew J. Breitwisch
IPC分类号： H01L47/00 , H01L45/00 , H01L27/24
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A memory device includes a plurality of side-wall electrodes formed on a first side-wall of a trench within an insulating layer over a first plurality of contacts in an array of contacts in a substrate. The plurality of side-wall electrodes contact respective top surfaces of the first plurality of contacts. The side-wall electrodes respectively comprise a layer of tantalum nitride, having a composition TaxNy, where y is greater than x, and a layer of electrode material having a lower electrical resistivity and a lower thermal resistivity than the layer of tantalum nitride. Top surfaces of the plurality of side-wall electrodes contact memory material. A second plurality of side-wall electrodes may be formed on a second side-wall of the trench over a second plurality of contacts in the array of contacts.
摘要翻译：存储器件包括多个侧壁电极，形成在绝缘层中的沟槽的第一侧壁上，在衬底中的触点阵列中的第一多个触点上。多个侧壁电极接触第一多个触点的相应顶表面。侧壁电极分别包括氮化钽层，其具有组成为TaxNy，其中y大于x，并且电极材料层具有比氮化钽层更低的电阻率和更低的热阻率。多个侧壁电极的顶表面接触记忆材料。第二多个侧壁电极可以形成在沟槽阵列中的第二多个触点上的沟槽的第二侧壁上。

6. 发明授权

US08716759B2 Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device 有权
标题翻译：方法可以直接在扩展垫片下方定制峰值电场的位置，以提高快速移位装置的可编程性
公开(公告)号：US08716759B2
公开(公告)日：2014-05-06
申请号：US13430018
申请日：2012-03-26
申请人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
发明人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
IPC分类号： H01L29/76
CPC分类号： H01L29/66477 , H01L21/26513 , H01L21/26586 , H01L21/266 , H01L29/1083 , H01L29/6659 , H01L29/66833 , H01L29/7834 , H01L29/792
摘要： A prompt-shift device having reduced programming time in the sub-millisecond range is provided. The prompt-shift device includes an altered extension region located within said semiconductor substrate and on at least one side of the patterned gate region, and an altered halo region located within the semiconductor substrate and on at least one side of the patterned gate region. The altered extension region has an extension ion dopant concentration of less than about 1E20 atoms/cm3, and the altered extension region has a halo ion dopant concentration of greater than about 5E18 atoms/cm3. The altered halo region is in direct contact with the altered extension region.
摘要翻译：提供了在亚毫秒范围内减少编程时间的提示移位装置。快速移位装置包括位于所述半导体衬底内并且在图案化栅极区域的至少一侧上的改变的扩展区域，以及位于半导体衬底内以及位于图案化栅极区域的至少一侧的改变的卤素区域。改变的延伸区域具有小于约1E20原子/ cm3的延伸离子掺杂剂浓度，并且改变的延伸区域具有大于约5E18原子/ cm3的卤素离子掺杂剂浓度。改变的晕区与改变的延伸区直接接触。

7. 发明授权

US08633464B2 In via formed phase change memory cell with recessed pillar heater 失效
标题翻译：在通孔形成相位改变存储单元与凹柱加热器
公开(公告)号：US08633464B2
公开(公告)日：2014-01-21
申请号：US13350967
申请日：2012-01-16
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.
摘要翻译：一种用于制造包括多个通孔相变存储单元的相变存储器件的方法包括：形成由导电材料形成的支柱加热器，沿着与要连接到存取电路的导电触点阵列相对应的衬底的接触表面沿着围绕柱加热器的衬底的暴露区域形成电介质层，在电介质层之上形成层间电介质（ILD）层，将通孔蚀刻到电介质层，每个通孔对应于每个立柱加热器，使得上表面每个立柱加热器暴露在每个通孔内，使每个立柱加热器凹陷，在每个凹槽加热器上的每个通孔中沉积相变材料，使每个通孔内的相变材料凹陷，并且在相变材料上的通孔内形成顶部电极。

8. 发明授权

US08471236B2 Flat lower bottom electrode for phase change memory cell 失效
标题翻译：用于相变存储单元的平底下电极
公开(公告)号：US08471236B2
公开(公告)日：2013-06-25
申请号：US13550091
申请日：2012-07-16
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
IPC分类号： H01L29/40
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译：一种具有平底下电极的相变存储单元及其制造方法。该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极。

9. 发明授权

US08395192B2 Single mask adder phase change memory element 有权
标题翻译：单掩模加法器相变存储元件
公开(公告)号：US08395192B2
公开(公告)日：2013-03-12
申请号：US13004471
申请日：2011-01-11
申请人： Matthew J. Breitwisch , Chung Hon Lam
发明人： Matthew J. Breitwisch , Chung Hon Lam
IPC分类号： H01L29/76
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/143 , H01L45/144 , H01L45/1683 , H01L45/1691
摘要： A method of fabricating a phase change memory element within a semiconductor structure and a semiconductor structure having the same that includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region formed within a dielectric layer at a same layer within the semiconductor structure, depositing a conformal film within the opening and recessing the conformal film to expose the upper surface of the bottom electrode, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.
摘要翻译：一种制造半导体结构内的相变存储元件的方法以及具有这样的半导体结构的方法，该方法包括蚀刻对底部电极的上表面的开口，所述开口由与形成的金属区域的高度相等的高度形成在半导体结构内的相同层的电介质层内，在开口内沉积共形膜并使保形膜凹陷以暴露底部电极的上表面，将相变材料沉积在开口内，使相变材料在内打开并在凹陷相变材料上形成顶部电极。

10. 发明授权

US08344351B2 Phase change memory device with plated phase change material 有权
标题翻译：相变存储器件，具有电镀相变材料
公开(公告)号：US08344351B2
公开(公告)日：2013-01-01
申请号：US13159594
申请日：2011-06-14
申请人： Matthew J. Breitwisch , Eric A. Joseph , Alejandro G. Schrott , Xiaoyan Shao
发明人： Matthew J. Breitwisch , Eric A. Joseph , Alejandro G. Schrott , Xiaoyan Shao
IPC分类号： H01L29/04 , H01L47/00 , H01L29/06
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1608 , H01L45/1683 , H01L45/1691
摘要： A phase change memory device includes a plurality of memory cells comprising a substrate having a contact surface with an array of conductive contacts to be connected with access circuitry and a nitride layer formed at the contact surface. A plurality of vias are formed through the nitride layer to the contact surface and correspond to each conductive contact, the vias including a conformal conductive seed layer lining each via along exposed portions of the nitride layer and the contact surface and having oxidized edges. A dielectric layer is recessed within the conformal conductive seed layer and exposes a center region of each via. A phase change material is recessed within the center region of each via. A conductive material that remains conductive upon oxidation is formed over the phase change material. A top electrode is formed on each memory cell.
摘要翻译：相变存储器件包括多个存储单元，其包括具有与要与接触电路连接的导电触点阵列的接触表面的衬底和在接触表面形成的氮化物层。多个通孔通过氮化物层形成到接触表面并且对应于每个导电接触，通孔包括沿着氮化物层和接触表面的暴露部分并且具有氧化边缘的每个通孔衬里的共形导电种子层。电介质层凹入保形导电晶种层内并露出每个通孔的中心区域。相变材料凹陷在每个通孔的中心区域内。在相变材料上形成氧化时保持导电的导电材料。在每个存储单元上形成顶部电极。

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