专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07190007B2 Isolated fully depleted silicon-on-insulator regions by selective etch 失效
标题翻译：通过选择性蚀刻隔离完全耗尽的绝缘体上硅区域
公开(公告)号：US07190007B2
公开(公告)日：2007-03-13
申请号：US10710821
申请日：2004-08-05
申请人： Matthew J. Breitwisch , Chung H. Lam , Randy W. Mann , Dale W. Martin
发明人： Matthew J. Breitwisch , Chung H. Lam , Randy W. Mann , Dale W. Martin
IPC分类号： H01L29/47
CPC分类号： H01L21/764 , H01L21/76283 , H01L21/76289 , H01L29/78654
摘要： The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 Å.
摘要翻译：本发明提供一种形成超薄且均匀的Si层的方法，包括以下步骤：提供具有由绝缘区分隔开的半导体区域的衬底; 将掺杂剂注入衬底中以在半导体区域的上部含Si表面下方的半导体区域中提供蚀刻差分掺杂部分; 在包括半导体区域和绝缘区域的衬底中形成沟槽; 从所述半导体区域去除所述蚀刻差分掺杂部分以在所述半导体区域的上表面下方形成空腔; 以及用沟槽电介质填充所述沟槽，其中所述沟槽电介质材料包围在所述半导体区域的所述上部含Si表面之下的空腔。半导体区域的上部含Si表面具有小于约的均匀厚度。

2. 发明授权

US06881672B2 Selective silicide blocking 失效
标题翻译：选择性硅化物封闭
公开(公告)号：US06881672B2
公开(公告)日：2005-04-19
申请号：US10723700
申请日：2003-11-26
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/823871 , H01L21/823842
摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has silicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.
摘要翻译：本文公开了选择性硅化半导体结构及其制造方法。半导体结构在多晶硅线路上存在硅化物，N +扩散区域或N +有源区域与多晶硅线路的N + / P +结处的P +扩散区域或有源区域之间存在硅化物，而N +有源区域和P +活性区域上不存在硅化物区。这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

3. 发明授权

US06778449B2 Method and design for measuring SRAM array leakage macro (ALM) 失效
标题翻译： SRAM阵列泄漏宏（ALM）测量方法与设计
公开(公告)号：US06778449B2
公开(公告)日：2004-08-17
申请号：US10064302
申请日：2002-07-01
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Randy W. Mann , Jeffrey H. Oppold
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Randy W. Mann , Jeffrey H. Oppold
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5006
摘要： A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.
摘要翻译：用于具有通过导线连接在一起的单元阵列的测试结构的方法和结构。导线将电池连接在一起，就像它们是单个电池一样。导线可以包括通用字线; 一个普通的位线公共位线补码线，公共N阱电压线，公共内部地线，公共内部电压线和/或公共接地线。

4. 发明授权

US06700163B2 Selective silicide blocking 有权
标题翻译：选择性硅化物封闭
公开(公告)号：US06700163B2
公开(公告)日：2004-03-02
申请号：US09683278
申请日：2001-12-07
申请人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Terence B. Hook , Randy W. Mann , Christopher S. Putnam , Mohammad I. Younus
IPC分类号： H01L2976
CPC分类号： H01L21/823871 , H01L21/823842
摘要： A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has suicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.
摘要翻译：本文公开了选择性硅化半导体结构及其制造方法。半导体结构在N +扩散或N +有源区域之间的多晶硅线路上存在自杀，并且在多晶硅线路的N + / P +结处的P +扩散或有源区域存在自杀，并且在N +有源区域和P +活性区域上不存在硅化物区。这种选择性硅化的存在在多晶硅线的N +区和多晶硅线的P +区之间产生有益的低电阻连接。在N +和P +有源区，特别是PFET和NFET结构上不存在硅化，可防止与器件硅化相关的电流泄漏。

5. 发明授权

US08716759B2 Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device 有权
标题翻译：方法可以直接在扩展垫片下方定制峰值电场的位置，以提高快速移位装置的可编程性
公开(公告)号：US08716759B2
公开(公告)日：2014-05-06
申请号：US13430018
申请日：2012-03-26
申请人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
发明人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
IPC分类号： H01L29/76
CPC分类号： H01L29/66477 , H01L21/26513 , H01L21/26586 , H01L21/266 , H01L29/1083 , H01L29/6659 , H01L29/66833 , H01L29/7834 , H01L29/792
摘要： A prompt-shift device having reduced programming time in the sub-millisecond range is provided. The prompt-shift device includes an altered extension region located within said semiconductor substrate and on at least one side of the patterned gate region, and an altered halo region located within the semiconductor substrate and on at least one side of the patterned gate region. The altered extension region has an extension ion dopant concentration of less than about 1E20 atoms/cm3, and the altered extension region has a halo ion dopant concentration of greater than about 5E18 atoms/cm3. The altered halo region is in direct contact with the altered extension region.
摘要翻译：提供了在亚毫秒范围内减少编程时间的提示移位装置。快速移位装置包括位于所述半导体衬底内并且在图案化栅极区域的至少一侧上的改变的扩展区域，以及位于半导体衬底内以及位于图案化栅极区域的至少一侧的改变的卤素区域。改变的延伸区域具有小于约1E20原子/ cm3的延伸离子掺杂剂浓度，并且改变的延伸区域具有大于约5E18原子/ cm3的卤素离子掺杂剂浓度。改变的晕区与改变的延伸区直接接触。

6. 发明授权

US08633464B2 In via formed phase change memory cell with recessed pillar heater 失效
标题翻译：在通孔形成相位改变存储单元与凹柱加热器
公开(公告)号：US08633464B2
公开(公告)日：2014-01-21
申请号：US13350967
申请日：2012-01-16
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/143 , H01L27/2436 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.
摘要翻译：一种用于制造包括多个通孔相变存储单元的相变存储器件的方法包括：形成由导电材料形成的支柱加热器，沿着与要连接到存取电路的导电触点阵列相对应的衬底的接触表面沿着围绕柱加热器的衬底的暴露区域形成电介质层，在电介质层之上形成层间电介质（ILD）层，将通孔蚀刻到电介质层，每个通孔对应于每个立柱加热器，使得上表面每个立柱加热器暴露在每个通孔内，使每个立柱加热器凹陷，在每个凹槽加热器上的每个通孔中沉积相变材料，使每个通孔内的相变材料凹陷，并且在相变材料上的通孔内形成顶部电极。

7. 发明授权

US08471236B2 Flat lower bottom electrode for phase change memory cell 失效
标题翻译：用于相变存储单元的平底下电极
公开(公告)号：US08471236B2
公开(公告)日：2013-06-25
申请号：US13550091
申请日：2012-07-16
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
IPC分类号： H01L29/40
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译：一种具有平底下电极的相变存储单元及其制造方法。该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极。

8. 发明授权

US08310864B2 Self-aligned bit line under word line memory array 有权
标题翻译：字线内存阵列下的自对准位线
公开(公告)号：US08310864B2
公开(公告)日：2012-11-13
申请号：US12815680
申请日：2010-06-15
申请人： Hsiang-Lan Lung , Chung H Lam , Erh-Kun Lai , Matthew J. Breitwisch
发明人： Hsiang-Lan Lung , Chung H Lam , Erh-Kun Lai , Matthew J. Breitwisch
IPC分类号： G11C11/00
CPC分类号： H01L27/2454 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： A memory device is described that comprises a plurality of bit lines and an array of vertical transistors arranged on the plurality of bit lines. A plurality of word lines is formed along rows of vertical transistors in the array which comprise thin film sidewalls of word line material and arranged so that the thin film sidewalls merge in the row direction, and do not merge in the column direction, to form word lines. The word lines provide “surrounding gate” structures for embodiments in which the vertical transistors are field effect transistors. Memory elements are formed in electrical communication with the vertical transistors. A fully self-aligned process is provided in which the word lines and memory elements are aligned with the vertical transistors without additional patterning steps.
摘要翻译：描述了包括多个位线和布置在多个位线上的垂直晶体管阵列的存储器件。多个字线沿阵列中的垂直晶体管行形成，其中包括字线材料的薄膜侧壁，并且布置成使得薄膜侧壁在行方向上合并，并且不在列方向上合并，以形成字线条。对于其中垂直晶体管是场效应晶体管的实施例，字线提供周围的栅极结构。存储元件形成为与垂直晶体管电连通。提供了完全自对准的工艺，其中字线和存储元件与垂直晶体管对准，而没有额外的图案化步骤。

9. 发明授权

US08283650B2 Flat lower bottom electrode for phase change memory cell 有权
标题翻译：用于相变存储单元的平底下电极
公开(公告)号：US08283650B2
公开(公告)日：2012-10-09
申请号：US12550048
申请日：2009-08-28
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Hsiang-Lan Lung , Alejandro G. Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1683
摘要： A phase change memory cell having a flat lower bottom electrode and a method for fabricating the same. The method includes forming a dielectric layer over a substrate including an array of conductive contacts, patterning, a via having a low aspect ratio such that a depth of the via is less than a width thereof, to a contact surface of the substrate corresponding to each of the array of conductive contacts to be connected to access circuitry, etching the dielectric layer and depositing electrode material over the etched dielectric layer and within each via, and planarizing the electrode material to form a plurality of lower bottom electrodes on each of the conductive contacts.
摘要翻译：一种具有平底下电极的相变存储单元及其制造方法。该方法包括在包括导电触点阵列的基板上形成电介质层，图案化，具有低纵横比以使得通孔的深度小于其宽度的通孔到对应于每个的基板的接触表面导电触头的阵列阵列连接到存取电路，蚀刻电介质层并在蚀刻后的介电层上和每个通孔内沉积电极材料，并平面化电极材料，以在每个导电触头上形成多个下部底部电极。

10. 发明申请

US20120181627A1 METHOD TO TAILOR LOCATION OF PEAK ELECTRIC FIELD DIRECTLY UNDERNEATH AN EXTENSION SPACER FOR ENHANCED PROGRAMMABILITY OF A PROMPT-SHIFT DEVICE 审中-公开
公开(公告)号：US20120181627A1
公开(公告)日：2012-07-19
申请号：US13429930
申请日：2012-03-26
申请人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
发明人： Matthew J. Breitwisch , Roger W. Cheek , Jeffrey B. Johnson , Chung H. Lam , Beth A. Rainey , Michael J. Zierak
IPC分类号： H01L29/78
CPC分类号： H01L29/66477 , H01L21/26513 , H01L21/26546 , H01L21/26586 , H01L21/266 , H01L29/1083 , H01L29/6659 , H01L29/66833 , H01L29/7834 , H01L29/792
摘要： A prompt-shift device having reduced programming time in the sub-millisecond range is provided. The prompt-shift device includes an altered extension region located within said semiconductor substrate and on at least one side of the patterned gate region, and an altered halo region located within the semiconductor substrate and on at least one side of the patterned gate region. The altered extension region has an extension ion dopant concentration of less than about 1E20 atoms/cm3, and the altered extension region has a halo ion dopant concentration of greater than about 5E18 atoms/cm3. The altered halo region is in direct contact with the altered extension region.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式