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1. 发明授权

US5774476A Timing apparatus and timing method for wrapper cell speed path testing of embedded cores within an integrated circuit 失效
标题翻译：集成电路内部嵌入式核心封装单元速度路径测试的定时装置和定时方法
公开(公告)号：US5774476A
公开(公告)日：1998-06-30
申请号：US794743
申请日：1997-02-03
申请人： Matthew D. Pressly , Grady L. Giles
发明人： Matthew D. Pressly , Grady L. Giles
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/31858
摘要： Wrapper cells (16 and 18) are coupled to inputs and outputs of an embedded core (14) within an integrated circuit (10). The wrapper cells (16 and 18) are used to test timing specifications of the embedded core after the embedded core has been integrated on-chip with other peripheral logic (12). In order to accurately measure the timing specifications, test circuits (FIGS. 6-8) are formed on chip with the wrapper where the test circuits are used to measure clock skew a like internal integrated circuit (IC) parameters. The clock skew and other measured internal IC parameters are used to accurately test the timing specification of the embedded core with reduced uncertainty.
摘要翻译：封装单元（16和18）耦合到集成电路（10）内的嵌入式芯（14）的输入和输出。封装单元（16和18）用于在嵌入式内核与其他外设逻辑（12）集成在一起后，测试嵌入式内核的时序规范。为了精确地测量时序规范，测试电路（图6-8）与封装件在芯片上形成，其中测试电路用于测量类似内部集成电路（IC）参数的时钟偏移。时钟偏移和其他测量的内部IC参数用于精确测试嵌入式核心的时序规范，降低不确定性。

2. 发明授权

US5889788A Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation 失效
标题翻译：嵌入式单元架构，用于嵌入式核心微处理器的路径延迟测试和操作方法
公开(公告)号：US5889788A
公开(公告)日：1999-03-30
申请号：US794742
申请日：1997-02-03
申请人： Matthew D. Pressly , Grady L. Giles , Alfred L. Crouch
发明人： Matthew D. Pressly , Grady L. Giles , Alfred L. Crouch
IPC分类号： G01R31/3185 , G06F11/267 , G06F11/00
CPC分类号： G06F11/2236 , G01R31/31858
摘要： An integrated circuit contains customer specified logic (12), an embedded core (14), and a plurality of speed path test cells (16 and 18). Once the core (14) is embedded within an integrated circuit (10), not all of the input and output terminals of the embedded core are available at external terminals of the integrated circuit (10). Therefore, the wrapper speed path test cells (16 and 18) are provided. The cell (16) contains two flip-flops (20 and 22) which can be used to launch logic transitions into the embedded core (14) to perform two clock speed path testing. The cell (18) contains flip-flops (26 and 28) which can perform a speed path launch operations to a customer specified logic (12). The cell (16) can perform speed path capture operations for the customer specified logic (12) whereas the cell (18) can perform speed path capture operations for the embedded core (14).
摘要翻译：集成电路包含客户指定的逻辑（12），嵌入式核心（14）和多个速度路径测试单元（16和18）。一旦核心（14）嵌入在集成电路（10）内，嵌入式核心的所有输入和输出端子都不能在集成电路（10）的外部端子处可用。因此，提供了包装速度路径测试单元（16和18）。单元（16）包含两个触发器（20和22），其可以用于启动到嵌入式核心（14）的逻辑转换以执行两个时钟速度路径测试。单元（18）包含可以向客户指定的逻辑（12）执行速度路径发射操作的触发器（26和28）。小区（16）可以为客户指定的逻辑（12）执行速度路径捕获操作，而小区（18）可以对嵌入式核心（14）执行速度路径捕获操作。

3. 发明授权

US08103924B2 Test access mechanism for multi-core processor or other integrated circuit 有权
标题翻译：多核处理器或其他集成电路的测试访问机制
公开(公告)号：US08103924B2
公开(公告)日：2012-01-24
申请号：US12021455
申请日：2008-01-29
申请人： Grady L. Giles , Brian Hoang , Timothy J. Wood
发明人： Grady L. Giles , Brian Hoang , Timothy J. Wood
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318544 , G01R31/318572 , G06F11/2236
摘要： A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one of the plurality of processor cores. The pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel, and a compare channel. Each pipeline stage is operable to convey commands to its corresponding processor core via the command channel, to convey scan input data to its corresponding processor core via the SDI channel, to receive scan output data conveyed from the corresponding processor core to the SDO channel and the compare channel, and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data.
摘要翻译：具有流水线测试访问机制（TAM）的处理器。处理器包括多个处理器核心。每个处理器核心包括包括多个串联扫描元件的扫描链。处理器还包括流水线TAM，流水线TAM包括多个流水线级，每个流水线对应于多个处理器核心之一。流水线TAM包括命令通道，扫描数据输入（SDI）通道，扫描数据输出（SDO）通道和比较通道。每个流水线级可操作以经由命令通道将命令传送到其对应的处理器核心，以经由SDI信道将扫描输入数据传送到其对应的处理器核心，以接收从相应处理器核心传送到SDO通道的扫描输出数据，比较通道，并通过比较通道向下游传送比较数据，其中比较数据基于扫描输出数据。

4. 发明授权

US5220526A Method and apparatus for indicating a duplication of entries in a content addressable storage device 失效
标题翻译：用于指示内容可寻址存储设备中的条目的重复的方法和装置
公开(公告)号：US5220526A
公开(公告)日：1993-06-15
申请号：US662610
申请日：1991-03-01
申请人： Grady L. Giles , Yui K. Ho , Robert B. Cohen
发明人： Grady L. Giles , Yui K. Ho , Robert B. Cohen
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： An apparatus (10) indicates a duplication of information stored in a content addressable memory (CAM 12) system at the time the information is written to the system. In the CAM system, Match line signals (Match 0-Match (N-1) are asserted when information being written to a predetermined row is identical to information previously stored in the system. However, the Match line signal associated with the predetermined row is disabled by a predetermined transistor (14, 16, 18, 20) when the row is written. Because information is simultaneously presented in parallel to other rows in the CAM system, a Match line signal is asserted if the information currently written to the predetermined row is identical to information previously written to another row in the CAM system. Any asserted Match line signal which was not disabled indicates to the user of the CAM system that two or more entries are identical in the CAM array.
摘要翻译：当信息被写入系统时，装置（10）指示存储在内容可寻址存储器（CAM 12）系统中的信息的复制。在CAM系统中，当写入预定行的信息与先前存储在系统中的信息相同时，匹配线信号（匹配0匹配（N-1））被置位，然而，与预定行相关联的匹配线信号是当行被写入时由预定晶体管（14,16,18,20）禁止，因为与CAM系统中的其他行同时呈现信息，所以如果当前写入预定行的信息则匹配线信号被断言与先前写入CAM系统中的另一行的信息相同，任何未被禁用的断言的匹配线信号向CAM系统的用户指示CAM阵列中两个或多个条目相同。

5. 发明授权

US5015875A Toggle-free scan flip-flop 失效
标题翻译：无切换扫描触发器
公开(公告)号：US5015875A
公开(公告)日：1991-05-14
申请号：US444208
申请日：1989-12-01
申请人： Grady L. Giles , Jesse R. Wilson
发明人： Grady L. Giles , Jesse R. Wilson
IPC分类号： G06F11/267
CPC分类号： G06F11/2236
摘要： A toggle-free scan flip-flop (TFSFF) is provided which is designed for use during a test mode scan operation. The toggle-free scan flip-flop has the capability of not toggling its parallel output during test mode scan operation. The TFSFF uses a master latch, which is controlled by a scan multiplexor, to selectively update two alternate slave latches. Switching logic controls the determination of which alternate slave latch is updated with the incoming data signal. An existent scan enable (SE) signal controls the switching logic, and thus, the TFSFF design requires no additional control signals for its operation. During the scan test mode, the data is clocked through the TFSFF from a Scan-Data-In terminal, and out the Scan-Data-Out terminal, without affecting the system data output Q. The shift sequence is followed by a capture interval, during which the Q output is automatically updated with the desired data to test the target logic. Thus, the logic under test is not affected by the loading of the scan test vector, since the parallel system output Q of the TFSFF does not toggle during the shifting sequence.
摘要翻译：提供无切换扫描触发器（TFSFF），其设计用于在测试模式扫描操作期间使用。无触发扫描触发器在测试模式扫描操作期间具有不切换其并行输出的能力。 TFSFF使用由扫描多路复用器控制的主锁存器来选择性地更新两个备用从器件锁存器。开关逻辑控制使用输入数据信号更新哪个备用从锁存器的确定。现有的扫描使能（SE）信号控制开关逻辑，因此，TFSFF设计不需要其操作的附加控制信号。在扫描测试模式期间，数据通过TFSFF从扫描数据输入端输出，并输出扫描数据输出端，而不影响系统数据输出Q.移位序列后跟一个捕获间隔，在此期间，使用所需数据自动更新Q输出以测试目标逻辑。因此，被测逻辑不受扫描测试向量的加载的影响，因为TFSFF的并行系统输出Q在移位序列期间不会切换。

6. 发明授权

US07925937B2 Apparatus for testing embedded memory read paths 有权
标题翻译：用于测试嵌入式存储器读取路径的装置
公开(公告)号：US07925937B2
公开(公告)日：2011-04-12
申请号：US11970018
申请日：2008-01-07
申请人： Joel T. Irby , Grady L. Giles , Alexander W. Schaefer , Gregory A. Constant , Floyd L. Dankert , Amy M. Novak
发明人： Joel T. Irby , Grady L. Giles , Alexander W. Schaefer , Gregory A. Constant , Floyd L. Dankert , Amy M. Novak
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/32 , G11C2029/0401 , G11C2029/3202
摘要： An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.
摘要翻译：集成电路。集成电路包括多个逻辑电路。集成电路还包括包括串联耦合的多个扫描元件的扫描链，其中扫描链被配置为加载要施加到逻辑电路进行测试的刺激数据。扫描链还被配置为在施加刺激数据之后捕获数据。集成电路还包括具有读取端口的嵌入式存储器，其中读取端口经由读取路径耦合到多个逻辑电路中的一个或多个。嵌入式存储器包括具有多个扫描可控存储元件的虚拟条目。在测试期间，虚拟条目可操作以将转换数据应用于读取路径，以便在读取路径中的一个或多个逻辑电路中引起逻辑状态转换。

7. 发明申请

US20090193303A1 TEST ACCESS MECHANISM FOR MULTI-CORE PROCESSOR OR OTHER INTEGRATED CIRCUIT 有权
标题翻译：多核处理器或其他集成电路的测试访问机制
公开(公告)号：US20090193303A1
公开(公告)日：2009-07-30
申请号：US12021455
申请日：2008-01-29
申请人： Grady L. Giles , Brian Hoang , Timothy J. Wood
发明人： Grady L. Giles , Brian Hoang , Timothy J. Wood
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318536 , G01R31/318544 , G01R31/318572 , G06F11/2236
摘要： A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one of the plurality of processor cores. The pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel, and a compare channel. Each pipeline stage is operable to convey commands to its corresponding processor core via the command channel, to convey scan input data to its corresponding processor core via the SDI channel, to receive scan output data conveyed from the corresponding processor core to the SDO channel and the compare channel, and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data.
摘要翻译：具有流水线测试访问机制（TAM）的处理器。处理器包括多个处理器核心。每个处理器核心包括包括多个串联扫描元件的扫描链。处理器还包括流水线TAM，流水线TAM包括多个流水线级，每个流水线对应于多个处理器核心之一。流水线TAM包括命令通道，扫描数据输入（SDI）通道，扫描数据输出（SDO）通道和比较通道。每个流水线级可操作以经由命令通道将命令传送到其对应的处理器核心，以经由SDI信道将扫描输入数据传送到其对应的处理器核心，以接收从相应处理器核心传送到SDO通道的扫描输出数据，比较通道，并通过比较通道向下游传送比较数据，其中比较数据基于扫描输出数据。

8. 发明申请

US20090177934A1 APPARATUS FOR TESTING EMBEDDED MEMORY READ PATHS 有权
标题翻译：用于测试嵌入式存储器读取PATHS的装置
公开(公告)号：US20090177934A1
公开(公告)日：2009-07-09
申请号：US11970018
申请日：2008-01-07
申请人： Joel T. Irby , Grady L. Giles , Alexander W. Schaefer , Gregory A. Constant , Floyd D. Dankert , Amy M. Novak
发明人： Joel T. Irby , Grady L. Giles , Alexander W. Schaefer , Gregory A. Constant , Floyd D. Dankert , Amy M. Novak
IPC分类号： G01R31/28 , G06F11/25
CPC分类号： G11C29/32 , G11C2029/0401 , G11C2029/3202
摘要： An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.
摘要翻译：集成电路。集成电路包括多个逻辑电路。集成电路还包括包括串联耦合的多个扫描元件的扫描链，其中扫描链被配置为加载要施加到逻辑电路进行测试的刺激数据。扫描链还被配置为在施加刺激数据之后捕获数据。集成电路还包括具有读取端口的嵌入式存储器，其中读取端口经由读取路径耦合到多个逻辑电路中的一个或多个。嵌入式存储器包括具有多个扫描可控存储元件的虚拟条目。在测试期间，虚拟条目可操作以将转换数据应用于读取路径，以便在读取路径中的一个或多个逻辑电路中引起逻辑状态转换。

9. 发明授权

US5812561A Scan based testing of an integrated circuit for compliance with timing specifications 失效
标题翻译：基于扫描的集成电路测试，以符合定时规范
公开(公告)号：US5812561A
公开(公告)日：1998-09-22
申请号：US707272
申请日：1996-09-03
申请人： Grady L. Giles , Alfred Larry Crouch , Odis Dale Amason, Jr. , Matthew Donald Pressly , Clark Gilson Shepard , Michael Alan Mateja , Lee Allen Corley , Daniel T. Marquette , Jason E. Doege
发明人： Grady L. Giles , Alfred Larry Crouch , Odis Dale Amason, Jr. , Matthew Donald Pressly , Clark Gilson Shepard , Michael Alan Mateja , Lee Allen Corley , Daniel T. Marquette , Jason E. Doege
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318572 , G01R31/31858
摘要： A method and implementation for providing an improved testable design for an integrated circuit (IC) device. The integrated circuit includes a functional path for the implementation of a functional specification as well as a testing path for testing the timing specifications for the integrated circuit. Input switching devices are connected between input terminals of the IC and inputs to sequential circuit elements, for example flip-flop devices, in the IC. Similarly, output switching devices are connected between outputs of the flip-flop devices and output terminals of the IC. The switching devices are selectively operable to alternately connect the flip-flop devices into either a functional IC path for providing functional output signals during functional cycles, or into a testing IC path for providing testing output signals indicative of timing points throughout the IC during testing cycles. The IC is also operable to selectively disable tristate bus drivers during the testing cycles. The switching devices are arranged such that a single output terminal of the IC may be selectively used to provide both functional and testing output signals.
摘要翻译：一种为集成电路（IC）设备提供改进的可测试设计的方法和实现。集成电路包括用于实现功能规范的功能路径以及用于测试集成电路的时序规范的测试路径。输入开关器件连接在IC的输入端子和IC之间的时序电路元件（例如触发器器件）上。类似地，输出开关器件连接在触发器件的输出端和IC的输出端子之间。切换装置可选择性地可操作以将触发器装置交替地连接到用于在功能周期期间提供功能输出信号的功能IC路径，或者用于在测试周期期间提供指示整个IC的定时点的测试输出信号的测试IC路径。该IC还可用于在测试周期期间选择性地禁用三态总线驱动器。开关器件被布置成使得IC的单个输出端子可以被选择性地用于提供功能和测试输出信号。

10. 发明授权

US5369752A Method and apparatus for shifting data in an array of storage elements in a data processing system 失效
标题翻译：用于在数据处理系统中的存储元件阵列中的数据移位的方法和装置
公开(公告)号：US5369752A
公开(公告)日：1994-11-29
申请号：US891241
申请日：1992-06-01
申请人： Grady L. Giles , William D. Atwell, Jr. , Jesse R. Wilson , Richard B. Reis
发明人： Grady L. Giles , William D. Atwell, Jr. , Jesse R. Wilson , Richard B. Reis
IPC分类号： G11C7/10 , G11C29/32 , G06F12/02
CPC分类号： G11C7/1006 , G11C29/32
摘要： A method and apparatus for shifting data in an array of storage elements (22-37) in a data processing system (10). In one form, the present invention uses multiplexer (MUX) logic (38) and Shift Control signals to selectively couple storage elements (22-37) to latches (39-42). In this manner, data values can be serially scanned into and out of the array for test purposes without requiring a duplicate set of latches. The MUX logic 38 couples one storage element (22-37) to each latch (39-42). Then MUX logic 38 decouples those storage elements (22-37). Next, MUX logic 38 couples an adjacent storage element (22-37) to each latch (39-42). In this manner, the storage elements (22-37) in one row and the latches (39-42) mimic the functionality of a shift register.
摘要翻译：一种用于在数据处理系统（10）中的存储元件阵列（22-37）中移位数据的方法和装置。在一种形式中，本发明使用多路复用器（MUX）逻辑（38）和移位控制信号来选择性地将存储元件（22-37）耦合到锁存器（39-42）。以这种方式，数据值可以串行扫描进出阵列用于测试目的，而不需要重复的锁存器组。 MUX逻辑38将一个存储元件（22-37）耦合到每个锁存器（39-42）。然后MUX逻辑38解耦这些存储元件（22-37）。接下来，MUX逻辑38将相邻存储元件（22-37）耦合到每个锁存器（39-42）。以这种方式，一行中的存储元件（22-37）和锁存器（39-42）模拟移位寄存器的功能。

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