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    • 2. 发明申请
    • METHOD FOR FAST PARALLEL INSTRUCTION LENGTH DETERMINATION
    • 用于快速并行指示长度确定的方法
    • US20120066478A1
    • 2012-03-15
    • US12878456
    • 2010-09-09
    • Robert B. Cohen
    • Robert B. Cohen
    • G06F9/312
    • G06F9/30152
    • The present invention provides a method and apparatus that may be used for parallel instruction length decoding. One embodiment of the method includes concurrently determining a plurality of masks identifying bytes in a plurality of candidate instructions. Each mask uses a different byte in a first fetch window as a starting byte and the corresponding one of the plurality of candidate instructions includes the starting byte. This embodiment of the method also includes selecting one of the masks to identify one of the candidate instructions as a first instruction using information indicating an ending byte of a previous instruction.
    • 本发明提供了可以用于并行指令长度解码的方法和装置。 该方法的一个实施例包括同时确定识别多个候选指令中的字节的多个掩码。 每个掩码在第一取出窗口中使用不同的字节作为起始字节,并且多个候选指令中的对应的一个包括起始字节。 该方法的该实施例还包括选择掩模之一以使用指示先前指令的结束字节的信息来将候选指令之一识别为第一指令。
    • 3. 发明授权
    • Method and apparatus for indicating a duplication of entries in a
content addressable storage device
    • 用于指示内容可寻址存储设备中的条目的重复的方法和装置
    • US5220526A
    • 1993-06-15
    • US662610
    • 1991-03-01
    • Grady L. GilesYui K. HoRobert B. Cohen
    • Grady L. GilesYui K. HoRobert B. Cohen
    • G11C15/00
    • G11C15/00
    • An apparatus (10) indicates a duplication of information stored in a content addressable memory (CAM 12) system at the time the information is written to the system. In the CAM system, Match line signals (Match 0-Match (N-1) are asserted when information being written to a predetermined row is identical to information previously stored in the system. However, the Match line signal associated with the predetermined row is disabled by a predetermined transistor (14, 16, 18, 20) when the row is written. Because information is simultaneously presented in parallel to other rows in the CAM system, a Match line signal is asserted if the information currently written to the predetermined row is identical to information previously written to another row in the CAM system. Any asserted Match line signal which was not disabled indicates to the user of the CAM system that two or more entries are identical in the CAM array.
    • 当信息被写入系统时,装置(10)指示存储在内容可寻址存储器(CAM 12)系统中的信息的复制。 在CAM系统中,当写入预定行的信息与先前存储在系统中的信息相同时,匹配线信号(匹配0匹配(N-1))被置位,然而,与预定行相关联的匹配线信号是 当行被写入时由预定晶体管(14,16,18,20)禁止,因为与CAM系统中的其他行同时呈现信息,所以如果当前写入预定行的信息则匹配线信号被断言 与先前写入CAM系统中的另一行的信息相同,任何未被禁用的断言的匹配线信号向CAM系统的用户指示CAM阵列中两个或多个条目相同。
    • 5. 发明授权
    • Paged memory management unit which locks translators in translation
cache if lock specified in translation table
    • 分页存储器管理单元,如果在转换表中指定了锁定,则可以将翻译器锁定在翻译缓存中
    • US4727485A
    • 1988-02-23
    • US815613
    • 1986-01-02
    • William M. KeshlearRobert B. Cohen
    • William M. KeshlearRobert B. Cohen
    • G06F12/10G06F12/12
    • G06F12/126G06F12/1027
    • In a data processing system, a paged memory management unit (PMMU) translates logical addresses provided by a processor to physical addresses in a memory using translators constructed from page descriptors comprising, in part, translation tables stored in the memory. The PMMU maintains a set of recently used translators in a translator cache. In response to a particular lock value contained in a lock field of the page descriptor for a particular page, the PMMU sets a lock indicator in the translator cache associated with the corresponding translator, to preclude replacement of this translator in the translator cache. A lock warning mechanism provides a lock warning signal whenever all but a predetermined number of the translators in the cache are locked. In response, the PMMU can warn the processor that the translator cache is in danger of becoming full of locked translators. Preferably, the PMMU is also inhibited from locking the last translator in the cache.
    • 在数据处理系统中,分页存储器管理单元(PMMU)将由处理器提供的逻辑地址转换为存储器中的物理地址,该译码器包括部分由存储在存储器中的转换表构成的页描述符。 PMMU在翻译缓存中维护一组最近使用的翻译器。 响应于特定页面的页面描述符的锁定字段中包含的特定锁定值,PMMU在与对应的翻译器相关联的翻译器高速缓存器中设置锁定指示符,以排除在翻译器高速缓存中替换该翻译器。 只要高速缓存中的预定数量的转换器都被锁定,锁定警告机制就会提供锁定警告信号。 作为响应,PMMU可以警告处理器翻译器缓存有变得充满锁定的翻译器的危险。 优选地,PMMU也被禁止锁定高速缓存中的最后一个转换器。