会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 4. 发明授权
    • Multiple master inter integrated circuit bus system
    • 多主集成电路总线系统
    • US07281070B2
    • 2007-10-09
    • US11045682
    • 2005-01-28
    • Matthew D. BomhoffBrian J. CagnoRobert A. KuboGregg S. Lucas
    • Matthew D. BomhoffBrian J. CagnoRobert A. KuboGregg S. Lucas
    • G06F12/00G06F11/00H04J3/24G06F15/16
    • G06F13/4286Y02D10/14Y02D10/151
    • A multiple-master Inter Integrated Circuit (“I2C”) bus system includes a first master device including a first processing device within a first power boundary and a second master device including a second processing device within a second power boundary connected through a single I2C bus to one or more slave devices. The second master device utilizes a software algorithm or hardware component to detect or manage power up of the first power boundary. Additionally, the second master device includes a bus control algorithm that allows it, once initiated, to communicate with the connected slave device, to direct the first power boundary to activate or detect that the first power boundary has powered up, and to release the I2C bus. Once the first processor has initialized, the first master device acquires control of the I2C bus without arbitration or interference with the second master device.
    • 多主集成电路(“I2C”)总线系统包括第一主设备,其包括第一电源边界内的第一处理设备和第二主设备,第二主设备包括通过单个连接的第二电源边界内的第二处理设备 I 2 C总线到一个或多个从设备。 第二主设备利用软件算法或硬件组件来检测或管理第一功率边界的上电。 此外,第二主设备包括总线控制算法,其允许其一旦被启动与所连接的从设备进行通信,以引导第一功率边界来激活或检测到第一功率边界已通电,并释放I 2 C总线。 一旦第一处理器被初始化,第一主设备获得对I2C总线的控制,而不与第二主设备进行仲裁或干扰。
    • 7. 发明授权
    • Verifying data integrity of a non-volatile memory system during data caching process
    • 在数据缓存过程中验证非易失性存储器系统的数据完整性
    • US08037380B2
    • 2011-10-11
    • US12169273
    • 2008-07-08
    • Brian J. CagnoJohn C. ElliottRobert A. KuboGregg S. Lucas
    • Brian J. CagnoJohn C. ElliottRobert A. KuboGregg S. Lucas
    • G11C29/00G06F13/00
    • G06F11/1064G11C29/56G11C2029/0407
    • To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I2C register that is monitored by the storage controller. The storage controller may determine that the non-volatile flash is functional without any defects, and the controller may remove power from the non-volatile flash to extend its reliability. Periodically, in the background, the controller may run diagnostic routines to detect any failures associated with the volatile memory and the controller itself.
    • 为了确保非易失性闪存的完整性,控制器使用背景测试模式对非易失性存储器进行编程,并在上电自检(POST)操作期间验证非易失性存储器。 结合验证非易失性存储器,控制器可以定期地将诊断和状态报告给存储控制器。 作为存储控制器上电程序的一部分,存储控制器通过由存储控制器监视的I2C寄存器向控制器发出POST命令。 存储控制器可以确定非易失性闪存在没有任何缺陷的情况下起作用,并且控制器可以从非易失性闪存移除电力以扩展其可靠性。 定期地,在后台,控制器可以运行诊断例程来检测与易失性存储器和控制器本身相关联的任何故障。