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1. 发明授权

US07423964B2 Apparatus and method to set the signaling rate of a network disposed within an information storage and retrieval system 失效
标题翻译：设置信息存储和检索系统中设置的网络的信令速率的装置和方法
公开(公告)号：US07423964B2
公开(公告)日：2008-09-09
申请号：US10993768
申请日：2004-11-18
申请人： Matthew D. Bomhoff , Brian J. Cagno , John C. Elliott , Carl E. Jones , Robert A. Kubo , Gregg S. Lucas , Katherine S. Tyldesley
发明人： Matthew D. Bomhoff , Brian J. Cagno , John C. Elliott , Carl E. Jones , Robert A. Kubo , Gregg S. Lucas , Katherine S. Tyldesley
IPC分类号： G01R31/08
CPC分类号： H04L41/0896
摘要： A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed.
摘要翻译：公开了一种设置网络速度的方法。该方法提供与系统控制器和多个交换机域互连的网络，其中这些多个交换机域中的每一个包括一个或多个信息存储设备和交换机域控制器，并且由多个交换机域中的每一个设置信令该交换机域的速率。所述方法由所述系统控制器对所述交换机域的信令速率的所述多个交换机域中的每一个进行带内查询，并且通过所述多个交换机域中的每一个提供所述交换机域的信令速率的带内。该方法由系统控制器向系统控制器提供指定第一网络速度的第一速度选择命令，并且由多个交换机域中的每一个将该交换机域的信令速率复位到第一网络速度。

2. 发明授权

US07974189B2 Apparatus and method to set the signaling rate of a network disposed within an information storage and retrieval system 失效
标题翻译：设置信息存储和检索系统中设置的网络的信令速率的装置和方法
公开(公告)号：US07974189B2
公开(公告)日：2011-07-05
申请号：US12196155
申请日：2008-08-21
申请人： Matthew D. Bomhoff , Brian J. Cagno , John C. Elliott , Carl E. Jones , Robert A. Kubo , Gregg S. Lucas , Katherine S. Tyldesley
发明人： Matthew D. Bomhoff , Brian J. Cagno , John C. Elliott , Carl E. Jones , Robert A. Kubo , Gregg S. Lucas , Katherine S. Tyldesley
IPC分类号： G01R31/08
CPC分类号： H04L41/0896
摘要： A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed.
摘要翻译：公开了一种设置网络速度的方法。该方法提供与系统控制器和多个交换机域互连的网络，其中这些多个交换机域中的每一个包括一个或多个信息存储设备和交换机域控制器，并且由多个交换机域中的每一个设置信令该交换机域的速率。所述方法由所述系统控制器对所述交换机域的信令速率的所述多个交换机域中的每一个进行带内查询，并且通过所述多个交换机域中的每一个提供所述交换机域的信令速率的带内。该方法由系统控制器向系统控制器提供指定第一网络速度的第一速度选择命令，并且由多个交换机域中的每一个将该交换机域的信令速率复位到第一网络速度。

3. 发明授权

US07535832B2 Apparatus and method to set the signaling rate of a switch domain disposed within an information storage and retrieval system 失效
标题翻译：设置信息存储和检索系统中设置的交换机域的信令速率的装置和方法
公开(公告)号：US07535832B2
公开(公告)日：2009-05-19
申请号：US10995459
申请日：2004-11-22
申请人： Matthew D. Bomhoff , Brian J. Cagno , John C. Elliott , Carl E. Jones , Robert A. Kubo , Gregg S. Lucas
发明人： Matthew D. Bomhoff , Brian J. Cagno , John C. Elliott , Carl E. Jones , Robert A. Kubo , Gregg S. Lucas
IPC分类号： H04L12/26
CPC分类号： G06F13/4022 , G06F3/061 , G06F3/0632 , G06F3/0635 , G06F3/0683
摘要： A method is disclosed to set the signaling rate of a switch domain disposed in an information storage and retrieval system. The method establishes a switch domain target operating speed, and determines if that switch domain target operating speed comprises a first signaling rate. If the switch domain target operating speed comprises a first signaling rate, then the method asserts first Device Control Code bits to each of the plurality of data storage devices, and each of the plurality of data storage devices communicates with the switch using that first signaling rate. If the switch domain target operating speed does not comprise the first signaling rate, then the method asserts second Device Control Code bits to each of the plurality of data storage devices, and each of the plurality of data storage devices communicates with the switch using a second signaling rate.
摘要翻译：公开了一种设置信息存储和检索系统中设置的交换机域的信令速率的方法。该方法建立交换机域目标操作速度，并确定交换机域目标操作速度是否包括第一信令速率。如果切换域目标操作速度包括第一信令速率，则该方法将第一设备控制代码位置为多个数据存储设备中的每一个，并且多个数据存储设备中的每一个与该交换机使用该第一信令速率。如果切换域目标操作速度不包括第一信令速率，则该方法将第二设备控制代码位置为多个数据存储设备中的每一个，并且多个数据存储设备中的每一个使用第二信令速率与交换机通信信号速率。

4. 发明授权

US07281070B2 Multiple master inter integrated circuit bus system 有权
标题翻译：多主集成电路总线系统
公开(公告)号：US07281070B2
公开(公告)日：2007-10-09
申请号：US11045682
申请日：2005-01-28
申请人： Matthew D. Bomhoff , Brian J. Cagno , Robert A. Kubo , Gregg S. Lucas
发明人： Matthew D. Bomhoff , Brian J. Cagno , Robert A. Kubo , Gregg S. Lucas
IPC分类号： G06F12/00 , G06F11/00 , H04J3/24 , G06F15/16
CPC分类号： G06F13/4286 , Y02D10/14 , Y02D10/151
摘要： A multiple-master Inter Integrated Circuit (“I2C”) bus system includes a first master device including a first processing device within a first power boundary and a second master device including a second processing device within a second power boundary connected through a single I2C bus to one or more slave devices. The second master device utilizes a software algorithm or hardware component to detect or manage power up of the first power boundary. Additionally, the second master device includes a bus control algorithm that allows it, once initiated, to communicate with the connected slave device, to direct the first power boundary to activate or detect that the first power boundary has powered up, and to release the I2C bus. Once the first processor has initialized, the first master device acquires control of the I2C bus without arbitration or interference with the second master device.
摘要翻译：多主集成电路（“I2C”）总线系统包括第一主设备，其包括第一电源边界内的第一处理设备和第二主设备，第二主设备包括通过单个连接的第二电源边界内的第二处理设备 I 2 C总线到一个或多个从设备。第二主设备利用软件算法或硬件组件来检测或管理第一功率边界的上电。此外，第二主设备包括总线控制算法，其允许其一旦被启动与所连接的从设备进行通信，以引导第一功率边界来激活或检测到第一功率边界已通电，并释放I 2 C总线。一旦第一处理器被初始化，第一主设备获得对I2C总线的控制，而不与第二主设备进行仲裁或干扰。

5. 发明授权

US08161310B2 Extending and scavenging super-capacitor capacity 有权
标题翻译：扩展和清除超级电容器容量
公开(公告)号：US08161310B2
公开(公告)日：2012-04-17
申请号：US12099373
申请日：2008-04-08
申请人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
发明人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
IPC分类号： G06F11/30
CPC分类号： G06F1/28 , G11C5/141 , G11C11/4074
摘要： A memory system has mechanisms for scavenging capacity of a super capacitor by removing, or reducing, system load from the super capacitor when the super capacitor voltage decays below a low threshold. The mechanisms then restore the system load to the super capacitor when the super capacitor voltage ramps back above a high threshold. A controller may reduce system load by placing a volatile memory system in a standby state and disabling a field effect transistor to remove power from a non-volatile memory system. A controller may adjust the high threshold and/or a low threshold by setting a digitally controlled potentiometer in a threshold detect circuit via an I2C bus.
摘要翻译：存储器系统具有通过在超级电容器电压降低到低阈值以下时从超级电容器中去除或降低系统负载来清除超级电容器容量的机制。当超级电容器电压升高到高阈值以上时，机制将系统负载恢复到超级电容器。控制器可以通过将易失性存储器系统置于待机状态并且禁用场效应晶体管来从非易失性存储器系统去除功率来降低系统负载。控制器可以通过经由I2C总线在门限检测电路中设置数字控制的电位器来调节高阈值和/或低阈值。

6. 发明授权

US08093868B2 In situ verification of capacitive power support 有权
标题翻译：电容电源支持的原位验证
公开(公告)号：US08093868B2
公开(公告)日：2012-01-10
申请号：US12204456
申请日：2008-09-04
申请人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
发明人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
IPC分类号： H01M10/44 , H01M10/46
CPC分类号： G01R31/3634 , G01R31/028 , G06F12/0804 , G06F12/0866 , G06F2212/2228 , H02J7/345
摘要： A mechanism for in situ verification of capacitive power support is provided. A memory system uses a super capacitor to support a voltage rail when input power is lost or interrupted. The voltage discharge curve is a function of load and capacitance of the component. By stepping the regulated power supply to a lower output within the voltage range and recording voltage and current draw at the super capacitor as it discharges to the new regulator output voltage, the super capacitor holdup capability can be tested.
摘要翻译：提供了一种用于电容性电源支持的原位验证的机制。当输入电源丢失或中断时，存储器系统使用超级电容器来支持电压轨。电压放电曲线是组件的负载和电容的函数。通过在电压范围内将稳压电源降到较低的输出，并在超级电容释放到新的稳压器输出电压时记录电压和电流，可以测试超级电容器的保持能力。

7. 发明申请

US20100052625A1 In Situ Verification of Capacitive Power Support 有权
标题翻译：电容式电源支持的原位验证
公开(公告)号：US20100052625A1
公开(公告)日：2010-03-04
申请号：US12204456
申请日：2008-09-04
申请人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
发明人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
IPC分类号： H02J7/00
CPC分类号： G01R31/3634 , G01R31/028 , G06F12/0804 , G06F12/0866 , G06F2212/2228 , H02J7/345
摘要： A mechanism for in situ verification of capacitive power support is provided. A memory system uses a super capacitor to support a voltage rail when input power is lost or interrupted. The voltage discharge curve is a function of load and capacitance of the component. By stepping the regulated power supply to a lower output within the voltage range and recording voltage and current draw at the super capacitor as it discharges to the new regulator output voltage, the super capacitor holdup capability can be tested.
摘要翻译：提供了一种用于电容性电源支持的原位验证的机制。当输入电源丢失或中断时，存储器系统使用超级电容器来支持电压轨。电压放电曲线是组件的负载和电容的函数。通过在电压范围内将稳压电源降到较低的输出，并在超级电容释放到新的稳压器输出电压时记录电压和电流，可以测试超级电容器的保持能力。

8. 发明授权

US08037380B2 Verifying data integrity of a non-volatile memory system during data caching process 有权
标题翻译：在数据缓存过程中验证非易失性存储器系统的数据完整性
公开(公告)号：US08037380B2
公开(公告)日：2011-10-11
申请号：US12169273
申请日：2008-07-08
申请人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
发明人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
IPC分类号： G11C29/00 , G06F13/00
CPC分类号： G06F11/1064 , G11C29/56 , G11C2029/0407
摘要： To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I2C register that is monitored by the storage controller. The storage controller may determine that the non-volatile flash is functional without any defects, and the controller may remove power from the non-volatile flash to extend its reliability. Periodically, in the background, the controller may run diagnostic routines to detect any failures associated with the volatile memory and the controller itself.
摘要翻译：为了确保非易失性闪存的完整性，控制器使用背景测试模式对非易失性存储器进行编程，并在上电自检（POST）操作期间验证非易失性存储器。结合验证非易失性存储器，控制器可以定期地将诊断和状态报告给存储控制器。作为存储控制器上电程序的一部分，存储控制器通过由存储控制器监视的I2C寄存器向控制器发出POST命令。存储控制器可以确定非易失性闪存在没有任何缺陷的情况下起作用，并且控制器可以从非易失性闪存移除电力以扩展其可靠性。定期地，在后台，控制器可以运行诊断例程来检测与易失性存储器和控制器本身相关联的任何故障。

9. 发明申请

US20090254772A1 Extending and Scavenging Super-Capacitor Capacity 有权
标题翻译：扩展和清除超级电容器容量
公开(公告)号：US20090254772A1
公开(公告)日：2009-10-08
申请号：US12099373
申请日：2008-04-08
申请人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
发明人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
IPC分类号： G06F1/28 , G11C5/14
CPC分类号： G06F1/28 , G11C5/141 , G11C11/4074
摘要： A memory system has mechanisms for scavenging capacity of a super capacitor by removing, or reducing, system load from the super capacitor when the super capacitor voltage decays below a low threshold. The mechanisms then restore the system load to the super capacitor when the super capacitor voltage ramps back above a high threshold. A controller may reduce system load by placing a volatile memory system in a standby state and disabling a field effect transistor to remove power from a non-volatile memory system. A controller may adjust the high threshold and/or a low threshold by setting a digitally controlled potentiometer in a threshold detect circuit via an I2C bus.
摘要翻译：存储器系统具有通过在超级电容器电压降低到低阈值以下时从超级电容器中去除或降低系统负载来清除超级电容器容量的机制。当超级电容器电压升高到高阈值以上时，机制将系统负载恢复到超级电容器。控制器可以通过将易失性存储器系统置于待机状态并且禁用场效应晶体管来从非易失性存储器系统去除功率来降低系统负载。控制器可以通过经由I2C总线在门限检测电路中设置数字控制的电位器来调节高阈值和/或低阈值。

10. 发明申请

US20100011261A1 Verifying Data Integrity of a Non-Volatile Memory System during Data Caching Process 有权
标题翻译：在数据缓存过程中验证非易失性存储器系统的数据完整性
公开(公告)号：US20100011261A1
公开(公告)日：2010-01-14
申请号：US12169273
申请日：2008-07-08
申请人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
发明人： Brian J. Cagno , John C. Elliott , Robert A. Kubo , Gregg S. Lucas
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G06F11/1064 , G11C29/56 , G11C2029/0407
摘要： To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I2C register that is monitored by the storage controller. The storage controller may determine that the non-volatile flash is functional without any defects, and the controller may remove power from the non-volatile flash to extend its reliability. Periodically, in the background, the controller may run diagnostic routines to detect any failures associated with the volatile memory and the controller itself.
摘要翻译：为了确保非易失性闪存的完整性，控制器使用背景测试模式对非易失性存储器进行编程，并在上电自检（POST）操作期间验证非易失性存储器。结合验证非易失性存储器，控制器可以定期地将诊断和状态报告给存储控制器。作为存储控制器上电程序的一部分，存储控制器通过由存储控制器监视的I2C寄存器向控制器发出POST命令。存储控制器可以确定非易失性闪存在没有任何缺陷的情况下起作用，并且控制器可以从非易失性闪存移除电力以扩展其可靠性。定期地，在后台，控制器可以运行诊断例程来检测与易失性存储器和控制器本身相关联的任何故障。

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