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1. 发明授权

US09608922B2 Traffic control on an on-chip network 有权
公开(公告)号：US09608922B2
公开(公告)日：2017-03-28
申请号：US13993575
申请日：2011-12-23
申请人： Matteo Monchiero , Javier Carretero Casado , Enric Herrero Abellanas , Tanausu Ramirez , Xavier Vera
发明人： Matteo Monchiero , Javier Carretero Casado , Enric Herrero Abellanas , Tanausu Ramirez , Xavier Vera
IPC分类号： H04L12/24 , H04L12/825 , G06F15/78
CPC分类号： H04L47/25 , G06F15/7825 , H04L47/263 , Y02D10/12 , Y02D10/13 , Y02D50/10
摘要： An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.

2. 发明申请

US20140010079A1 TRAFFIC CONTROL ON AN ON-CHIP NETWORK 有权
标题翻译：一个片上网络的交通控制
公开(公告)号：US20140010079A1
公开(公告)日：2014-01-09
申请号：US13993575
申请日：2011-12-23
申请人： Matteo Monchiero , Javier Carretero Casado , Enric Herrero Abellanas , Tanausu Ramirez , Xavier Vera
发明人： Matteo Monchiero , Javier Carretero Casado , Enric Herrero Abellanas , Tanausu Ramirez , Xavier Vera
IPC分类号： H04L12/825
CPC分类号： H04L47/25 , G06F15/7825 , H04L47/263 , Y02D10/12 , Y02D10/13 , Y02D50/10
摘要： An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.
摘要翻译：一种用于控制片上网络上的业务的装置，系统和方法。该方法的实施例包括通过耦合到片上网络的第一节点将分组以第一速率注入到片上网络，在耦合到片上网络的第二节点处接收分组，修改响应于确定分组被注入到片上网络的速率应该改变，由第二节点分组，将具有由第二节点修改的比特的分组返回到第一节点，并且将第一速率改变第一节点响应于检测到分组中的比特被修改。

3. 发明申请

US20140258805A1 SELECTIVE PROVISION OF ERROR CORRECTION FOR MEMORY 有权
标题翻译：选择性提供存储器的错误校正
公开(公告)号：US20140258805A1
公开(公告)日：2014-09-11
申请号：US13792117
申请日：2013-03-10
申请人： Javier Carretero Casado , Xavier Vera , Daniel Sanchez , Tanausu Ramirez , Enric Herrero Abellanas , Nicholas Axelos
发明人： Javier Carretero Casado , Xavier Vera , Daniel Sanchez , Tanausu Ramirez , Enric Herrero Abellanas , Nicholas Axelos
IPC分类号： H03M13/35
CPC分类号： H03M13/35 , G06F11/1012
摘要： Embodiments of apparatuses, methods, and storage medium associated with selectively providing error correction to memory are disclosed herein. In one instance, an apparatus may include a memory controller configured to control access to a non-volatile memory having storage locations. The controller may be configured to provide a first error correction arrangement to provide a first level of error correction capability for data stored in the non-volatile memory. The memory controller may include a control/error correction block configured to provide a second error correction arrangement with a second level of error correction capability for data stored in the non-volatile memory. The second level of error correction capability enables correction of at least one bit error more than the first level. The memory controller may be configured to selectively employ the second error correction arrangement to complement the first error correction arrangement. Other embodiments may be described and claimed.
摘要翻译：本文公开了与选择性地向存储器提供错误校正相关联的装置，方法和存储介质的实施例。在一种情况下，装置可以包括被配置为控制对具有存储位置的非易失性存储器的访问的存储器控制器。控制器可以被配置为提供第一纠错装置，以便为存储在非易失性存储器中的数据提供第一级的纠错能力。存储器控制器可以包括控制/错误校正块，其被配置为向存储在非易失性存储器中的数据提供具有第二级纠错能力的第二纠错装置。第二级的纠错能力能够比第一级别更正至少一位误差。存储器控制器可以被配置为选择性地使用第二纠错装置来补充第一纠错装置。可以描述和要求保护其他实施例。

4. 发明授权

US09112537B2 Content-aware caches for reliability 有权
标题翻译：内容感知缓存可靠性
公开(公告)号：US09112537B2
公开(公告)日：2015-08-18
申请号：US13992504
申请日：2011-12-22
申请人： Tanausu Ramirez , Javier Carretero Casado , Enric Herrero , Matteo Monchiero , Xavier Vera
发明人： Tanausu Ramirez , Javier Carretero Casado , Enric Herrero , Matteo Monchiero , Xavier Vera
IPC分类号： H03M13/29 , G06F11/10 , G06F1/32 , H03M13/09 , H03M13/35 , G06F12/08
CPC分类号： H03M13/2906 , G06F1/3275 , G06F1/3296 , G06F11/1064 , G06F12/0895 , H03M13/09 , H03M13/356 , Y02D10/14 , Y02D10/172
摘要： Embodiments of systems, apparatuses, and methods for reducing data cache power consumption and error protection overhead are described. In some embodiments, the data cache is partitioned into cache portions. Each cache portion stores data that has a different fault tolerance and uses a different type of error detection mechanism than the other cache portions.
摘要翻译：描述了用于降低数据高速缓存功耗和错误保护开销的系统，设备和方法的实施例。在一些实施例中，数据高速缓存被分割成高速缓存部分。每个缓存部分存储具有不同容错的数据，并且使用与其它高速缓存部分不同的错误检测机制。

5. 发明申请

US20140237018A1 TRACKING DISTRIBUTED EXECUTION ON ON-CHIP MULTINODE NETWORKS WITHOUT A CENTRALIZED MECHANISM 审中-公开
标题翻译：在没有集中化机制的情况下跟踪片上多线程网络的分布式执行
公开(公告)号：US20140237018A1
公开(公告)日：2014-08-21
申请号：US13993313
申请日：2011-12-23
申请人： Matteo Monchiero , Javier Carretero Casado , Enric Herrero , Tanausu Ramirez , Xavier Vera
发明人： Matteo Monchiero , Javier Carretero Casado , Enric Herrero , Tanausu Ramirez , Xavier Vera
IPC分类号： H04L12/24
CPC分类号： H04L41/046 , G06F15/7825
摘要： A method and system for tracking distributed execution on on-chip multinode networks, the method comprising: initiating, by a first node coupled to an on-chip network, execution of instructions on the first node for a distributed agent; initiating, by the first node, execution of instructions on a second node coupled to the on-chip network for the distributed agent; initiating, by the second node, execution of instructions on a third node coupled to the on-chip network for the distributed agent, wherein the second node does not notify the first node of the initiated execution on the third node; providing reoccurring notification by the second and third nodes to all nodes coupled to the on-chip network that they continue to execute instructions for the distributed agent; and determining, by the first node, that execution of instructions for the distributed agent is complete by detecting an absence of reoccurring notifications from nodes the network.
摘要翻译：一种用于跟踪片上多节点网络上的分布式执行的方法和系统，所述方法包括：由耦合到片上网络的第一节点发起用于分布式代理的所述第一节点上的指令的执行; 由所述第一节点发起在耦合到所述分布式代理的片上网络的第二节点上执行指令; 由所述第二节点发起在所述分布式代理上耦合到所述片上网络的第三节点上的指令的执行，其中所述第二节点不在所述第三节点上通知所述第一节点所述发起的执行; 提供由第二和第三节点向连接到片上网络的所有节点重发的通知，他们继续执行分发代理的指令; 以及由所述第一节点通过检测不存在来自所述网络的节点的再发送的通知来确定所述分布式代理的指令的执行是否完成。

6. 发明授权

US09405647B2 Register error protection through binary translation 有权
标题翻译：通过二进制转换来注册错误保护
公开(公告)号：US09405647B2
公开(公告)日：2016-08-02
申请号：US13994697
申请日：2011-12-30
申请人： Xavier Vera , Javier Carretero Casado , Matteo Monchiero , Tanausu Ramirez , Enric Herrero
发明人： Xavier Vera , Javier Carretero Casado , Matteo Monchiero , Tanausu Ramirez , Enric Herrero
IPC分类号： G06F11/00 , G06F11/263 , G06F9/45
CPC分类号： G06F11/263 , G06F8/52 , G06F9/3013 , G06F11/004
摘要： Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.
摘要翻译：至少部分地基于由二进制翻译器翻译的代码的至少一个代码段，一些实现提供用于检测具有比阈值周期长的寿命的寄存器值的技术和布置。对于被检测为寿命长于阈值周期的寄存器值，至少一个在寄存器值的寿命期间使检测到的寄存器值的访问的指令可以包括在至少一个转换的代码段中，以由二进制翻译器

7. 发明申请

US20130318401A1 REGISTER ERROR PROTECTION THROUGH BINARY TRANSLATION 有权
标题翻译：通过二进制翻译进行注册错误保护
公开(公告)号：US20130318401A1
公开(公告)日：2013-11-28
申请号：US13994697
申请日：2011-12-30
申请人： Xavier Vera , Javier Carretero Casado , Matteo Monchiero , Tanausu Ramirez , Enric Herrero
发明人： Xavier Vera , Javier Carretero Casado , Matteo Monchiero , Tanausu Ramirez , Enric Herrero
IPC分类号： G06F11/263
CPC分类号： G06F11/263 , G06F8/52 , G06F9/3013 , G06F11/004
摘要： Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.
摘要翻译：至少部分地基于由二进制翻译器翻译的代码的至少一个代码段，一些实现提供用于检测具有比阈值周期长的寿命的寄存器值的技术和布置。对于被检测为寿命长于阈值周期的寄存器值，至少一个在寄存器值的寿命期间使检测到的寄存器值的访问的指令可以包括在至少一个转换的代码段中，以由二进制翻译器

8. 发明授权

US09286172B2 Fault-aware mapping for shared last level cache (LLC) 有权
标题翻译：共享最后一级缓存（LLC）的故障识别映射
公开(公告)号：US09286172B2
公开(公告)日：2016-03-15
申请号：US13995358
申请日：2011-12-22
申请人： Tanausu Ramirez , Javier Carretero Casado , Enric Herrero , Matteo Monchiero , Xavier Vera
发明人： Tanausu Ramirez , Javier Carretero Casado , Enric Herrero , Matteo Monchiero , Xavier Vera
IPC分类号： G06F11/00 , G06F11/20 , G11C29/12 , G11C29/44 , G11C29/50 , G06F12/08 , G06F12/12 , G11C29/00 , G11C11/41 , G11C29/04
CPC分类号： G06F11/2053 , G06F12/0802 , G06F12/084 , G06F12/126 , G11C11/41 , G11C29/12005 , G11C29/4401 , G11C29/50 , G11C29/702 , G11C2029/0407 , G11C2029/5002 , G11C2029/5004 , Y02D10/13
摘要： Embodiments of systems, apparatuses, and methods for utilizing a faulty cache line in a cache are described. In some embodiments, a graphics processing unit is allowed to access a faulty cache line in the cache. A cache access request to access a faulty cache line from a central processing unit core is remapped to access a fault-free cache line.
摘要翻译：描述了用于在高速缓存中利用故障高速缓存行的系统，装置和方法的实施例。在一些实施例中，允许图形处理单元访问高速缓存中的故障高速缓存行。从中央处理单元核心访问故障高速缓存行的高速缓存访问请求被重新映射以访问无故障高速缓存行。

9. 发明授权

US09170947B2 Recovering from data errors using implicit redundancy 有权
标题翻译：使用隐式冗余从数据错误中恢复
公开(公告)号：US09170947B2
公开(公告)日：2015-10-27
申请号：US13992732
申请日：2011-12-29
申请人： Xavier Vera , Matteo Monchiero , Javier Carretero Casado , Enric Herrero , Tanausu Ramirez
发明人： Xavier Vera , Matteo Monchiero , Javier Carretero Casado , Enric Herrero , Tanausu Ramirez
IPC分类号： G06F13/00 , G06F12/08 , G06F11/00 , G06F11/08 , G06F11/16 , G06F12/12 , G06F11/20
CPC分类号： G06F12/0822 , G06F11/00 , G06F11/08 , G06F11/1666 , G06F11/20 , G06F12/0806 , G06F12/0815 , G06F12/0817 , G06F12/12 , G06F2212/1024 , G06F2212/1028 , G06F2212/1044 , Y02D10/13
摘要： Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.
摘要翻译：本文公开的一些实现方式提供了通过存储在高速缓存目录中的信息来恢复存储在由多个处理器共享的存储器中的数据的技术和装置。处理器的核心可以启动对位于核心可访问的第一高速缓存中的特定数据的访问（例如，读或写）。响应于检测到与访问特定数据相关联的错误，可以识别包括特定数据的处理器中的位置，并且可以将特定数据从该位置复制到第一高速缓存。

10. 发明申请

US20140089593A1 RECOVERING FROM DATA ERRORS USING IMPLICIT REDUNDANCY 有权
标题翻译：使用隐含的冗余恢复数据错误
公开(公告)号：US20140089593A1
公开(公告)日：2014-03-27
申请号：US13992732
申请日：2011-12-29
申请人： Xavier Vera , Matteo Monchiero , Javier Carretero Casado , Enric Herrero , Tanausu Ramirez
发明人： Xavier Vera , Matteo Monchiero , Javier Carretero Casado , Enric Herrero , Tanausu Ramirez
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0822 , G06F11/00 , G06F11/08 , G06F11/1666 , G06F11/20 , G06F12/0806 , G06F12/0815 , G06F12/0817 , G06F12/12 , G06F2212/1024 , G06F2212/1028 , G06F2212/1044 , Y02D10/13
摘要： Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.
摘要翻译：本文公开的一些实现方式提供了通过存储在高速缓存目录中的信息来恢复存储在由多个处理器共享的存储器中的数据的技术和装置。处理器的核心可以启动对位于核心可访问的第一高速缓存中的特定数据的访问（例如，读或写）。响应于检测到与访问特定数据相关联的错误，可以识别包括特定数据的处理器中的位置，并且可以将特定数据从该位置复制到第一高速缓存。

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