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1. 发明申请

WO2017071724A1 CALIBRATING A MEDIA ADVANCE SYSTEM OF A PAGE WIDE ARRAY PRINTING DEVICE 审中-公开
标题翻译：校正页宽印刷设备的介质前进系统
公开(公告)号：WO2017071724A1
公开(公告)日：2017-05-04
申请号：PCT/EP2015/002174
申请日：2015-10-30
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , BORREGO LEBRATO, Alberto , ROSES CONESA, Fco. Javier , TANAUSU,Ramirez , ISIDORO, Maya
发明人： BORREGO LEBRATO, Alberto , ROSES CONESA, Fco. Javier , TANAUSU,Ramirez , ISIDORO, Maya
IPC分类号： B41J11/42
CPC分类号： B41J11/42
摘要： A method of determining calibration values for a media advance system of a page wide array printing device is described. A test pattern is printed on a calibration medium which advances along a media axis through the printing device. The test pattern comprises a plurality of test marks. The test pattern is scanned along a scan axis using a sensor and the calibration medium is advanced along the media axis through the printing device. The dimensions of the scanned test marks are analyzed, and calibration values are determined from the analyzed dimensions of the test marks. The scan axis is orthogonal to the media axis.
摘要翻译：描述了确定页宽阵列打印装置的介质推进系统的校准值的方法。测试图案印刷在沿介质轴前进通过印刷装置的校准介质上。测试图案包括多个测试标记。使用传感器沿着扫描轴扫描测试图案，并且校准介质沿着介质轴线前进通过打印设备。分析扫描测试标记的尺寸，并根据测试标记的分析尺寸确定校准值。扫描轴与媒体轴正交。

2. 发明授权

US09608922B2 Traffic control on an on-chip network 有权
公开(公告)号：US09608922B2
公开(公告)日：2017-03-28
申请号：US13993575
申请日：2011-12-23
申请人： Matteo Monchiero , Javier Carretero Casado , Enric Herrero Abellanas , Tanausu Ramirez , Xavier Vera
发明人： Matteo Monchiero , Javier Carretero Casado , Enric Herrero Abellanas , Tanausu Ramirez , Xavier Vera
IPC分类号： H04L12/24 , H04L12/825 , G06F15/78
CPC分类号： H04L47/25 , G06F15/7825 , H04L47/263 , Y02D10/12 , Y02D10/13 , Y02D50/10
摘要： An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.

3. 发明申请

US20140019823A1 CONTENT-AWARE CACHES FOR RELIABILITY 审中-公开
标题翻译：内容可靠的高速缓存
公开(公告)号：US20140019823A1
公开(公告)日：2014-01-16
申请号：US13992504
申请日：2011-12-22
申请人： Tanausu Ramirez , Javier Carretero , Enric Herrero , Matteo Monchiero , Xavier Vera
发明人： Tanausu Ramirez , Javier Carretero , Enric Herrero , Matteo Monchiero , Xavier Vera
IPC分类号： H03M13/29
CPC分类号： H03M13/2906 , G06F1/3275 , G06F1/3296 , G06F11/1064 , G06F12/0895 , H03M13/09 , H03M13/356 , Y02D10/14 , Y02D10/172
摘要： Embodiments of systems, apparatuses, and methods for reducing data cache power consumption and error protection overhead are described. In some embodiments, the data cache is partitioned into cache portions. Each cache portion stores data that has a different fault tolerance and uses a different type of error detection mechanism than the other cache portions.
摘要翻译：描述了用于降低数据高速缓存功耗和错误保护开销的系统，设备和方法的实施例。在一些实施例中，数据高速缓存被分割成高速缓存部分。每个缓存部分存储具有不同容错的数据，并且使用与其它高速缓存部分不同的错误检测机制。

4. 发明授权

US09286172B2 Fault-aware mapping for shared last level cache (LLC) 有权
标题翻译：共享最后一级缓存（LLC）的故障识别映射
公开(公告)号：US09286172B2
公开(公告)日：2016-03-15
申请号：US13995358
申请日：2011-12-22
申请人： Tanausu Ramirez , Javier Carretero Casado , Enric Herrero , Matteo Monchiero , Xavier Vera
发明人： Tanausu Ramirez , Javier Carretero Casado , Enric Herrero , Matteo Monchiero , Xavier Vera
IPC分类号： G06F11/00 , G06F11/20 , G11C29/12 , G11C29/44 , G11C29/50 , G06F12/08 , G06F12/12 , G11C29/00 , G11C11/41 , G11C29/04
CPC分类号： G06F11/2053 , G06F12/0802 , G06F12/084 , G06F12/126 , G11C11/41 , G11C29/12005 , G11C29/4401 , G11C29/50 , G11C29/702 , G11C2029/0407 , G11C2029/5002 , G11C2029/5004 , Y02D10/13
摘要： Embodiments of systems, apparatuses, and methods for utilizing a faulty cache line in a cache are described. In some embodiments, a graphics processing unit is allowed to access a faulty cache line in the cache. A cache access request to access a faulty cache line from a central processing unit core is remapped to access a fault-free cache line.
摘要翻译：描述了用于在高速缓存中利用故障高速缓存行的系统，装置和方法的实施例。在一些实施例中，允许图形处理单元访问高速缓存中的故障高速缓存行。从中央处理单元核心访问故障高速缓存行的高速缓存访问请求被重新映射以访问无故障高速缓存行。

5. 发明申请

US20140189696A1 FAILURE RATE BASED CONTROL OF PROCESSORS 有权
标题翻译：基于失败率的处理器控制
公开(公告)号：US20140189696A1
公开(公告)日：2014-07-03
申请号：US13730822
申请日：2012-12-28
申请人： Enric H. Abellanas , Xavier Vera , Nicholas Axelos , Javier C. Casado , Tanausu Ramirez , Daniel Sanchez Pedreño
发明人： Enric H. Abellanas , Xavier Vera , Nicholas Axelos , Javier C. Casado , Tanausu Ramirez , Daniel Sanchez Pedreño
IPC分类号： G06F9/46
CPC分类号： G06F11/008 , G06F1/26 , G06F11/07 , G06F11/0703 , G06F11/0724
摘要： A method of an aspect includes determining a different operational configuration for each of a plurality of different maximum failure rates. Each of the different maximum failure rates corresponds to a different task of a plurality of tasks. The method also includes enforcing a plurality of logic each executing a different task of the plurality of tasks to operate according to the different corresponding determined operational configuration. Other methods, apparatus, and systems are also disclosed.
摘要翻译：一个方面的方法包括为多个不同的最大故障率中的每一个确定不同的操作配置。每个不同的最大故障率对应于多个任务的不同任务。该方法还包括执行多个逻辑，每个逻辑执行多个任务的不同任务，以根据不同的对应确定的操作配置进行操作。还公开了其它方法，装置和系统。

6. 发明申请

US20140189439A1 BANKING OF RELIABILITY METRICS 有权
标题翻译：可靠性度量标准
公开(公告)号：US20140189439A1
公开(公告)日：2014-07-03
申请号：US13729400
申请日：2012-12-28
申请人： Enric Herrero Abellanas , XAVIER VERA , JAVIER CARRETERO CASADO , TANAUSU RAMIREZ , NICHOLAS AXELOS , DANIEL SANCHEZ
发明人： Enric Herrero Abellanas , XAVIER VERA , JAVIER CARRETERO CASADO , TANAUSU RAMIREZ , NICHOLAS AXELOS , DANIEL SANCHEZ
IPC分类号： G06F11/00
CPC分类号： G06F11/008
摘要： In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric associated with the at least one functional block. The banking logic may also be to, if the average reliability metric exceeds a required level, implement a reduced reliability mode in the at least one functional block, where the reduced reliability mode is associated with a reduction in the average reliability metric. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个功能块和银行逻辑。银行业务逻辑可以是确定与至少一个功能块相关联的平均可靠性度量。如果平均可靠性度量超过所需等级，则银行业务逻辑也可以是在所述至少一个功能块中实现降低的可靠性模式，其中所述降低的可靠性模式与平均可靠性度量的降低相关联。描述和要求保护其他实施例。

7. 发明授权

US09405647B2 Register error protection through binary translation 有权
标题翻译：通过二进制转换来注册错误保护
公开(公告)号：US09405647B2
公开(公告)日：2016-08-02
申请号：US13994697
申请日：2011-12-30
申请人： Xavier Vera , Javier Carretero Casado , Matteo Monchiero , Tanausu Ramirez , Enric Herrero
发明人： Xavier Vera , Javier Carretero Casado , Matteo Monchiero , Tanausu Ramirez , Enric Herrero
IPC分类号： G06F11/00 , G06F11/263 , G06F9/45
CPC分类号： G06F11/263 , G06F8/52 , G06F9/3013 , G06F11/004
摘要： Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.
摘要翻译：至少部分地基于由二进制翻译器翻译的代码的至少一个代码段，一些实现提供用于检测具有比阈值周期长的寿命的寄存器值的技术和布置。对于被检测为寿命长于阈值周期的寄存器值，至少一个在寄存器值的寿命期间使检测到的寄存器值的访问的指令可以包括在至少一个转换的代码段中，以由二进制翻译器

8. 发明申请

US20140258805A1 SELECTIVE PROVISION OF ERROR CORRECTION FOR MEMORY 有权
标题翻译：选择性提供存储器的错误校正
公开(公告)号：US20140258805A1
公开(公告)日：2014-09-11
申请号：US13792117
申请日：2013-03-10
申请人： Javier Carretero Casado , Xavier Vera , Daniel Sanchez , Tanausu Ramirez , Enric Herrero Abellanas , Nicholas Axelos
发明人： Javier Carretero Casado , Xavier Vera , Daniel Sanchez , Tanausu Ramirez , Enric Herrero Abellanas , Nicholas Axelos
IPC分类号： H03M13/35
CPC分类号： H03M13/35 , G06F11/1012
摘要： Embodiments of apparatuses, methods, and storage medium associated with selectively providing error correction to memory are disclosed herein. In one instance, an apparatus may include a memory controller configured to control access to a non-volatile memory having storage locations. The controller may be configured to provide a first error correction arrangement to provide a first level of error correction capability for data stored in the non-volatile memory. The memory controller may include a control/error correction block configured to provide a second error correction arrangement with a second level of error correction capability for data stored in the non-volatile memory. The second level of error correction capability enables correction of at least one bit error more than the first level. The memory controller may be configured to selectively employ the second error correction arrangement to complement the first error correction arrangement. Other embodiments may be described and claimed.
摘要翻译：本文公开了与选择性地向存储器提供错误校正相关联的装置，方法和存储介质的实施例。在一种情况下，装置可以包括被配置为控制对具有存储位置的非易失性存储器的访问的存储器控制器。控制器可以被配置为提供第一纠错装置，以便为存储在非易失性存储器中的数据提供第一级的纠错能力。存储器控制器可以包括控制/错误校正块，其被配置为向存储在非易失性存储器中的数据提供具有第二级纠错能力的第二纠错装置。第二级的纠错能力能够比第一级别更正至少一位误差。存储器控制器可以被配置为选择性地使用第二纠错装置来补充第一纠错装置。可以描述和要求保护其他实施例。

9. 发明申请

US20130318401A1 REGISTER ERROR PROTECTION THROUGH BINARY TRANSLATION 有权
标题翻译：通过二进制翻译进行注册错误保护
公开(公告)号：US20130318401A1
公开(公告)日：2013-11-28
申请号：US13994697
申请日：2011-12-30
申请人： Xavier Vera , Javier Carretero Casado , Matteo Monchiero , Tanausu Ramirez , Enric Herrero
发明人： Xavier Vera , Javier Carretero Casado , Matteo Monchiero , Tanausu Ramirez , Enric Herrero
IPC分类号： G06F11/263
CPC分类号： G06F11/263 , G06F8/52 , G06F9/3013 , G06F11/004
摘要： Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.
摘要翻译：至少部分地基于由二进制翻译器翻译的代码的至少一个代码段，一些实现提供用于检测具有比阈值周期长的寿命的寄存器值的技术和布置。对于被检测为寿命长于阈值周期的寄存器值，至少一个在寄存器值的寿命期间使检测到的寄存器值的访问的指令可以包括在至少一个转换的代码段中，以由二进制翻译器

10. 发明申请

US20160011874A1 SILENT MEMORY INSTRUCTIONS AND MISS-RATE TRACKING TO OPTIMIZE SWITCHING POLICY ON THREADS IN A PROCESSING DEVICE 审中-公开
标题翻译：静音记忆指示和错误跟踪以优化加工设备中螺纹上的切换策略
公开(公告)号：US20160011874A1
公开(公告)日：2016-01-14
申请号：US14326879
申请日：2014-07-09
申请人： DORON ORENSTEIN , TOMER STARK , CHEN DAN , JACOB DOWECK , ENRIC G. CODINA , JOSEP M. CODINA , REKAI GONZALEZ-ALBERQUILLA , TANAUSU RAMIREZ
发明人： DORON ORENSTEIN , TOMER STARK , CHEN DAN , JACOB DOWECK , ENRIC G. CODINA , JOSEP M. CODINA , REKAI GONZALEZ-ALBERQUILLA , TANAUSU RAMIREZ
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3806 , G06F9/30043 , G06F9/30047 , G06F9/30058 , G06F9/30145 , G06F9/3017 , G06F9/3824 , G06F9/3836 , G06F9/3851 , G06F9/3861
摘要： A processing device implementing silent memory instructions and miss-rate tracking to optimize switching policy on threads is disclosed. A processing device of the disclosure includes a branch prediction unit (BPU) to predict that an instruction of a first thread in a current execution context of the processing device is a delinquent instruction, indicate that the first thread including the delinquent instruction is in a silent execution mode, indicate that the delinquent instruction is to be executed as a silent instruction, switch an execution context of the processing device to a second thread, and when the execution context returns to the first thread, cause the delinquent instruction to be re-executed as a regular instruction.
摘要翻译：公开了一种执行无声存储器指令和错误率跟踪以优化线程上的交换策略的处理设备。本公开的处理装置包括：分支预测单元（BPU），用于预测处理装置的当前执行上下文中的第一线程的指令是违规指令，指示包括不当指令的第一线程处于静默状态执行模式，指示作为无声指令执行拖欠指令，将处理装置的执行上下文切换到第二线程，并且当执行上下文返回到第一线程时，导致拖欠指令被重新执行作为常规教学。

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