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1. 发明授权

US09678878B2 Disabling cache portions during low voltage operations 有权
公开(公告)号：US09678878B2
公开(公告)日：2017-06-13
申请号：US13652480
申请日：2012-10-16
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08 , G06F12/126 , G06F12/0864 , G06F12/0804 , G06F1/32
CPC分类号： G06F12/0864 , G06F1/3243 , G06F12/0804 , G06F2212/1028 , Y02D10/13 , Y02D10/152
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

2. 发明授权

US09286172B2 Fault-aware mapping for shared last level cache (LLC) 有权
标题翻译：共享最后一级缓存（LLC）的故障识别映射
公开(公告)号：US09286172B2
公开(公告)日：2016-03-15
申请号：US13995358
申请日：2011-12-22
申请人： Tanausu Ramirez , Javier Carretero Casado , Enric Herrero , Matteo Monchiero , Xavier Vera
发明人： Tanausu Ramirez , Javier Carretero Casado , Enric Herrero , Matteo Monchiero , Xavier Vera
IPC分类号： G06F11/00 , G06F11/20 , G11C29/12 , G11C29/44 , G11C29/50 , G06F12/08 , G06F12/12 , G11C29/00 , G11C11/41 , G11C29/04
CPC分类号： G06F11/2053 , G06F12/0802 , G06F12/084 , G06F12/126 , G11C11/41 , G11C29/12005 , G11C29/4401 , G11C29/50 , G11C29/702 , G11C2029/0407 , G11C2029/5002 , G11C2029/5004 , Y02D10/13
摘要： Embodiments of systems, apparatuses, and methods for utilizing a faulty cache line in a cache are described. In some embodiments, a graphics processing unit is allowed to access a faulty cache line in the cache. A cache access request to access a faulty cache line from a central processing unit core is remapped to access a fault-free cache line.
摘要翻译：描述了用于在高速缓存中利用故障高速缓存行的系统，装置和方法的实施例。在一些实施例中，允许图形处理单元访问高速缓存中的故障高速缓存行。从中央处理单元核心访问故障高速缓存行的高速缓存访问请求被重新映射以访问无故障高速缓存行。

3. 发明申请

US20140189696A1 FAILURE RATE BASED CONTROL OF PROCESSORS 有权
标题翻译：基于失败率的处理器控制
公开(公告)号：US20140189696A1
公开(公告)日：2014-07-03
申请号：US13730822
申请日：2012-12-28
申请人： Enric H. Abellanas , Xavier Vera , Nicholas Axelos , Javier C. Casado , Tanausu Ramirez , Daniel Sanchez Pedreño
发明人： Enric H. Abellanas , Xavier Vera , Nicholas Axelos , Javier C. Casado , Tanausu Ramirez , Daniel Sanchez Pedreño
IPC分类号： G06F9/46
CPC分类号： G06F11/008 , G06F1/26 , G06F11/07 , G06F11/0703 , G06F11/0724
摘要： A method of an aspect includes determining a different operational configuration for each of a plurality of different maximum failure rates. Each of the different maximum failure rates corresponds to a different task of a plurality of tasks. The method also includes enforcing a plurality of logic each executing a different task of the plurality of tasks to operate according to the different corresponding determined operational configuration. Other methods, apparatus, and systems are also disclosed.
摘要翻译：一个方面的方法包括为多个不同的最大故障率中的每一个确定不同的操作配置。每个不同的最大故障率对应于多个任务的不同任务。该方法还包括执行多个逻辑，每个逻辑执行多个任务的不同任务，以根据不同的对应确定的操作配置进行操作。还公开了其它方法，装置和系统。

4. 发明申请

US20140189439A1 BANKING OF RELIABILITY METRICS 有权
标题翻译：可靠性度量标准
公开(公告)号：US20140189439A1
公开(公告)日：2014-07-03
申请号：US13729400
申请日：2012-12-28
申请人： Enric Herrero Abellanas , XAVIER VERA , JAVIER CARRETERO CASADO , TANAUSU RAMIREZ , NICHOLAS AXELOS , DANIEL SANCHEZ
发明人： Enric Herrero Abellanas , XAVIER VERA , JAVIER CARRETERO CASADO , TANAUSU RAMIREZ , NICHOLAS AXELOS , DANIEL SANCHEZ
IPC分类号： G06F11/00
CPC分类号： G06F11/008
摘要： In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric associated with the at least one functional block. The banking logic may also be to, if the average reliability metric exceeds a required level, implement a reduced reliability mode in the at least one functional block, where the reduced reliability mode is associated with a reduction in the average reliability metric. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个功能块和银行逻辑。银行业务逻辑可以是确定与至少一个功能块相关联的平均可靠性度量。如果平均可靠性度量超过所需等级，则银行业务逻辑也可以是在所述至少一个功能块中实现降低的可靠性模式，其中所述降低的可靠性模式与平均可靠性度量的降低相关联。描述和要求保护其他实施例。

5. 发明申请

US20140108733A1 DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS 审中-公开
标题翻译：在低电压运行期间禁用高速缓存部分
公开(公告)号：US20140108733A1
公开(公告)日：2014-04-17
申请号：US13652480
申请日：2012-10-16
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F1/3243 , G06F12/0804 , G06F2212/1028 , Y02D10/13 , Y02D10/152
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
摘要翻译：描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。还描述和要求保护其他实施例。

6. 发明授权

US08477558B2 Memory apparatuses with low supply voltages 有权
标题翻译：具有低电源电压的存储设备
公开(公告)号：US08477558B2
公开(公告)日：2013-07-02
申请号：US12262070
申请日：2008-10-30
申请人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio González
发明人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio González
IPC分类号： G11C8/00
CPC分类号： G06F13/4234 , G06F12/0802 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.
摘要翻译：提供了低电压存储装置。在一个实施例中，存储器装置包括存储器和存储器控制器。存储器控制器包括读控制器。读取控制器防止对存储器位置的读取操作在对存储器位置的写入操作之后至少N个时钟周期完成，其中N是在写入操作之后存储器位置稳定的时钟周期数。

7. 发明授权

US08352812B2 Protecting data storage structures from intermittent errors 有权
标题翻译：保护数据存储结构免受间歇性错误的影响
公开(公告)号：US08352812B2
公开(公告)日：2013-01-08
申请号：US11833765
申请日：2007-08-03
申请人： Xavier Vera , Jaume Abella , Javier Carretero Casado , Antonio González
发明人： Xavier Vera , Jaume Abella , Javier Carretero Casado , Antonio González
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G06F11/1405
摘要： Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected.
摘要翻译：公开了用于保护数据存储结构免于间歇性错误的装置和方法的实施例。在一个实施例中，装置包括多个数据存储位置，执行逻辑，错误检测逻辑和控制逻辑。执行逻辑是执行指令以生成数据值以存储在数据存储位置之一中。错误检测逻辑是检测数据存储位置中存储的数据值中的错误。控制逻辑是通过使执行逻辑重新执行用于重新生成数据值以存储在数据存储位置的指令来响应错误的检测，使得错误检测逻辑检查从数据读取的数据值存储位置，如果检测到另一个错误，则停用数据存储位置。

8. 发明申请

US20100115224A1 MEMORY APPARATUSES WITH LOW SUPPLY VOLTAGES 有权
标题翻译：具有低电压电压的存储器件
公开(公告)号：US20100115224A1
公开(公告)日：2010-05-06
申请号：US12262070
申请日：2008-10-30
申请人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio Gonzalez
发明人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio Gonzalez
IPC分类号： G06F12/02
CPC分类号： G06F13/4234 , G06F12/0802 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.
摘要翻译：提供了低电压存储装置。在一个实施例中，存储器装置包括存储器和存储器控制器。存储器控制器包括读控制器。读取控制器防止对存储器位置的读取操作在对存储器位置的写入操作之后至少N个时钟周期完成，其中N是在写入操作之后存储器位置稳定的时钟周期数。

9. 发明申请

US20090150653A1 Mechanism for soft error detection and recovery in issue queues 审中-公开
标题翻译：问题队列中的软错误检测和恢复机制
公开(公告)号：US20090150653A1
公开(公告)日：2009-06-11
申请号：US11999787
申请日：2007-12-07
申请人： Pedro Chaparro Monferrer , Xavier Vera , Jaume Abella , Javier Carretero Casado
发明人： Pedro Chaparro Monferrer , Xavier Vera , Jaume Abella , Javier Carretero Casado
IPC分类号： G06F9/22
CPC分类号： G06F9/321 , G06F9/3836 , G06F9/3838 , G06F9/3861 , G06F11/1008
摘要： In one embodiment, the present invention includes logic to detect a soft error occurring in certain stages of a core and recover from such error if detected. One embodiment may include logic to determine if a lapsed time from a last instruction to issue from an issue stage of a pipeline exceeds a threshold and if so to reset a dispatch table, as well as to determine if a parity error is detected in an entry of the dispatch table associated with an enqueued instruction and if so to prevent the enqueued instruction from issuance. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于检测在核心的某些阶段发生的软错误的逻辑，并且如果检测到则从该错误中恢复。一个实施例可以包括用于确定从流水线的发布阶段发出的最后一条指令的经过时间是否超过阈值的情况，并且如果是这样，则复位分派表，以及确定在条目中是否检测到奇偶校验错误与排队指令相关联的调度表，如果是这样，则防止发出排入的指令。描述和要求保护其他实施例。

10. 发明申请

US20090037781A1 CORRECTING INTERMITTENT ERRORS IN DATA STORAGE STRUCTURES 失效
标题翻译：纠正数据存储结构中的间断错误
公开(公告)号：US20090037781A1
公开(公告)日：2009-02-05
申请号：US11833784
申请日：2007-08-03
申请人： Jaume Abella , Javier Carretero Casado , Xavier Vera
发明人： Jaume Abella , Javier Carretero Casado , Xavier Vera
IPC分类号： G06F11/07
CPC分类号： G06F11/1064
摘要： Embodiments of apparatuses and methods for correcting intermittent errors in data storage structures are disclosed. In one embodiment, an apparatus includes a data storage location, error detection logic, inverting logic, control logic, operating logic, and evaluation logic. The error detection logic is to detect an error in a data value read from the data storage location. The inverting logic is to invert the erroneous data value to produce an inverted erroneous data value. The control logic is to cause the inverted erroneous data value to be stored in the data storage location and subsequently read from the data storage location to produce an operand value. The operating logic is to perform a logical operation using the erroneous data value and the operand value. The evaluation logic is to evaluate the result to determine if the error is a soft error.
摘要翻译：公开了用于校正数据存储结构中的间歇性错误的装置和方法的实施例。在一个实施例中，装置包括数据存储位置，错误检测逻辑，反相逻辑，控制逻辑，操作逻辑和评估逻辑。错误检测逻辑是检测从数据存储位置读取的数据值中的错误。反相逻辑是反转错误的数据值以产生反相的错误数据值。控制逻辑是使反转的错误数据值存储在数据存储位置，随后从数据存储位置读出以产生操作数值。操作逻辑是使用错误的数据值和操作数值来执行逻辑运算。评估逻辑是评估结果以确定误差是否为软错误。

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