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1. 发明申请

US20130135015A1 INTEGRATED CIRCUIT COMPRISING FRACTIONAL CLOCK MULTIPLICATION CIRCUITRY 有权
标题翻译：包含分时钟多路复用电路的集成电路
公开(公告)号：US20130135015A1
公开(公告)日：2013-05-30
申请号：US13686175
申请日：2012-11-27
申请人： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
发明人： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
IPC分类号： H03B19/00
CPC分类号： H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
摘要： Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
摘要翻译：描述能够通过使用注入锁定振荡器执行分数时钟倍增的电路。本文描述的一些实施例通过周期性地改变喷射位置，从喷射信号的一组注入位置周期性地改变喷射位置，和/或通过周期性地改变注入的注入信号的相位相位来改变相位进入国际劳工组织。

2. 发明授权

US08854091B2 Integrated circuit comprising fractional clock multiplication circuitry 有权
$Integrated circuit comprising fractional clock multiplication circuitry$
标题翻译：集成电路包括分数时钟乘法电路
公开(公告)号：US08854091B2
公开(公告)日：2014-10-07
申请号：US13686175
申请日：2012-11-27
申请人： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
发明人： Masum Hossain , Farshid Aryanfar , Mohammad Hekmat , Reza Navid
IPC分类号： H03B19/00 , H03K3/03 , H03K5/00
CPC分类号： H03B19/00 , G06F1/08 , G06F1/10 , H03K3/0315 , H03K5/00006 , H03L7/099
摘要： Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
摘要翻译：描述能够通过使用注入锁定振荡器执行分数时钟倍增的电路。本文描述的一些实施例通过周期性地改变喷射位置，从喷射信号的一组注入位置周期性地改变喷射位置，和/或通过周期性地改变注入的注入信号的相位相位来改变相位进入国际劳工组织。

3. 发明授权

US09094028B2 Wide range frequency synthesizer with quadrature generation and spur cancellation 有权
标题翻译：宽范围频率合成器具有正交发生和支线消除
公开(公告)号：US09094028B2
公开(公告)日：2015-07-28
申请号：US13830007
申请日：2013-03-14
申请人： Masum Hossain , Farshid Aryanfar
发明人： Masum Hossain , Farshid Aryanfar
IPC分类号： H03L7/06 , H03L7/23 , H03L7/08 , H03L7/081 , H03L7/099 , H03L7/18
CPC分类号： H03L7/235 , H03L7/0805 , H03L7/081 , H03L7/099 , H03L7/0995 , H03L7/18 , H03L7/23
摘要： A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.
摘要翻译：频率合成器从单个振荡器产生宽范围的频率，同时实现良好的噪声性能。级联锁相环（PLL）电路包括具有LC压控振荡器（VCO）的第一PLL电路和具有环形VCO的第二PLL电路。从第一PLL电路到第二PLL电路的前馈路径提供用于消除相位噪声的装置和信号路径，从而减少或消除杂散和量化效应。频率合成器可以直接产生同相和正交相输出信号。通过相位误差检测回路来控制分频环形VCO，以减少或消除正交信号之间的相位误差。

4. 发明授权

US08941420B2 Low-latency, frequency-agile clock multiplier 有权
标题翻译：低延迟，频率敏捷的时钟倍频器
公开(公告)号：US08941420B2
公开(公告)日：2015-01-27
申请号：US13983836
申请日：2012-05-24
申请人： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
发明人： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
IPC分类号： H03B19/00 , H03K5/00 , H03L7/06 , H03L7/099
CPC分类号： H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
摘要： In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
摘要翻译：在第一时钟频率倍增器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现基本上比孤立的国际劳工组织的输入频率范围更宽的集体输入频率范围。在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择时钟。

5. 发明申请

US20150078495A1 Clock and Data Recovery Having Shared Clock Generator 有权
标题翻译：具有共享时钟发生器的时钟和数据恢复
公开(公告)号：US20150078495A1
公开(公告)日：2015-03-19
申请号：US14371066
申请日：2012-03-13
申请人： Masum Hossain , Brian Leibowitz , Jihong Ren
发明人： Masum Hossain , Brian Leibowitz , Jihong Ren
IPC分类号： H04L7/00 , H04L27/32
CPC分类号： H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
摘要： This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
摘要翻译：本公开提供了一种用于多车道通信系统的时钟恢复电路。使用相应的本地CDR电路从输入信号恢复本地时钟，并且相关联的CDR错误信号被聚合或以其他方式组合。作为来自多个接收机的误差信号的组合的函数的可控振荡频率产生由本地CDR电路共享使用的全局恢复时钟。电压或电流控制延迟线还可用于相位调整全局恢复时钟，以减轻频带限制，车道相关，高频抖动。

6. 发明授权

US09577816B2 Clock and data recovery having shared clock generator 有权
标题翻译：具有共享时钟发生器的时钟和数据恢复
公开(公告)号：US09577816B2
公开(公告)日：2017-02-21
申请号：US14371066
申请日：2012-03-13
申请人： Masum Hossain , Brian Leibowitz , Jihong Ren
发明人： Masum Hossain , Brian Leibowitz , Jihong Ren
IPC分类号： H04L7/00 , H04L7/033 , H04L27/00 , H03L7/197 , H03L7/23 , H04L27/32
CPC分类号： H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
摘要： This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
摘要翻译：本公开提供了一种用于多车道通信系统的时钟恢复电路。使用相应的本地CDR电路从输入信号恢复本地时钟，并且相关联的CDR错误信号被聚合或以其他方式组合。作为来自多个接收机的误差信号的组合的函数的可控振荡频率产生由本地CDR电路共享使用的全局恢复时钟。电压或电流控制延迟线还可用于相位调整全局恢复时钟，以减轻频带限制，车道相关，高频抖动。

7. 发明申请

US20140035650A1 LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER 有权
标题翻译：低延迟，频率 - 时钟时钟乘法器
公开(公告)号：US20140035650A1
公开(公告)日：2014-02-06
申请号：US13983836
申请日：2012-05-24
申请人： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
发明人： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
IPC分类号： H03K5/00
CPC分类号： H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
摘要： In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
摘要翻译：在第一时钟频率倍增器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现基本上比孤立的国际劳工组织的输入频率范围更宽的集体输入频率范围。在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择时钟。

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