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1. 发明授权

US07986026B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US07986026B2
公开(公告)日：2011-07-26
申请号：US12707121
申请日：2010-02-17
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

2. 发明授权

US07663207B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07663207B2
公开(公告)日：2010-02-16
申请号：US11407323
申请日：2006-04-20
申请人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
发明人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.
摘要翻译：半导体器件包括具有MIM结构的电容器，通过该电容器提高器件的尺寸精度，并给出稳定的电容值。半导体器件100包括：半导体衬底102; 形成有MIM电容器的电容器形成区域130，其具有形成在半导体衬底102上的绝缘中间层104，第一电极110和第二电极112，并且第一电极110和第二电极112面向彼此通过绝缘夹层104; 以及屏蔽区域132，其包括形成在电容器形成区域130的外边缘中的多个屏蔽电极114，并且同时在与半导体衬底上的MIM电容器相同的层中设定预定电位 102，并且将电容器形成区域130与其他区域屏蔽。

3. 发明授权

US07414506B2 Semiconductor integrated circuit and fabrication method thereof 失效
标题翻译：半导体集成电路及其制作方法
公开(公告)号：US07414506B2
公开(公告)日：2008-08-19
申请号：US11017074
申请日：2004-12-21
申请人： Masayuki Furumiya , Ryota Yamamoto
发明人： Masayuki Furumiya , Ryota Yamamoto
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01F17/0006 , H01F41/046 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A multilayer interconnection layer is provided on a semiconductor substrate. An inductor is provided on an insulating layer that forms the uppermost layer of the multilayer interconnection layer. The inductor is formed by spirally arranging a single wiring. On the insulating layer, a multilayer structure body is provided in an inner region of the inductor. In the multilayer structure body, a plurality of ferromagnetic cores formed of Ni are arranged in a matrix. The height of each ferromagnetic core is equal to or larger than the width thereof.
摘要翻译：多层互连层设置在半导体衬底上。电感器设置在形成多层互连层的最上层的绝缘层上。电感器通过螺旋地布置单个布线而形成。在绝缘层上，在电感器的内部区域设置多层结构体。在多层结构体中，由Ni构成的多个铁磁性核排列成矩阵状。每个铁磁芯的高度等于或大于其宽度。

4. 发明授权

US07053165B2 Semiconductor integrated circuit including an inductor and method of manufacturing the same 有权
标题翻译：包括电感器的半导体集成电路及其制造方法
公开(公告)号：US07053165B2
公开(公告)日：2006-05-30
申请号：US10600104
申请日：2003-06-20
申请人： Masayuki Furumiya , Ryota Yamamoto
发明人： Masayuki Furumiya , Ryota Yamamoto
IPC分类号： H01L29/00
CPC分类号： H01L28/10 , H01F17/0006 , H01F27/34 , H01F41/046 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device, and method of manufacturing the same, includes an inductor with improved inductance and an improved quality factor (Q-factor) that can be miniaturized. In one example, an inductor (3) is provided on an insulating layer (2) of a multilayer interconnection layer (1). The inductor (3) is formed by a spiral arrangement of a wiring (3a). A lamination film (14) is provided in an internal region (13) of an inductor (3) on insulating layer (2), and can be formed by laminating a titanium-tungsten (TiW) layer (9), a copper (Cu) layer (10), a ferromagnetic substance layer (15) made of nickel (Ni), a Cu layer (11), and a TiW layer (12), in that order. A lower surface of ferromagnetic substance layer (15) can be lower than an upper surface of wiring layer (3a), and an upper surface of ferromagnetic substance layer (15) can be higher than a lower surface of wiring layer (3a). As a result, a lower portion of ferromagnetic substance layer (15) can be at the same layer (level) as wiring layer (3a). An upper surface of lamination film (14) can be made higher than a wiring layer (3a), and a lower surface of lamination film (14) can be made lower than a lower surface of a wiring layer (3a).
摘要翻译：半导体集成电路器件及其制造方法包括具有改善的电感的电感器和可以小型化的改进的品质因数（Q因子）。在一个示例中，电感器（3）设置在多层互连层（1）的绝缘层（2）上。电感器（3）由布线（3a）的螺旋布置形成。层叠膜（14）设置在绝缘层（2）上的电感器（3）的内部区域（13）中，并且可以通过层压钛 - 钨（TiW）层（9），铜（Cu ）层（10），由镍（Ni）制成的铁磁物质层（15），Cu层（11）和TiW层（12）。铁磁物质层（15）的下表面可以比布线层（3a）的上表面低，并且铁磁物质层（15）的上表面可以高于布线层（3a）的下表面，。结果，铁磁物质层（15）的下部可以与布线层（3a）处于相同的层（层）。层叠膜（14）的上表面可以比布线层（3a）高，并且层压膜（14）的下表面可以被制成低于布线层（3a）的下表面。

5. 发明申请

US20060087004A1 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
公开(公告)号：US20060087004A1
公开(公告)日：2006-04-27
申请号：US11247296
申请日：2005-10-12
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

6. 发明授权

US07432551B2 SOI semiconductor device including a guard ring region 有权
标题翻译： SOI半导体器件包括保护环区域
公开(公告)号：US07432551B2
公开(公告)日：2008-10-07
申请号：US11362132
申请日：2006-02-27
申请人： Ryota Yamamoto , Yutaka Akiyama , Masayuki Furumiya
发明人： Ryota Yamamoto , Yutaka Akiyama , Masayuki Furumiya
IPC分类号： H01L27/01
CPC分类号： H01L21/84 , H01L21/761 , H01L21/76251 , H01L21/765 , H01L27/1203
摘要： An object is to increase the amount of substrate noise absorbed in a guard ring, and to prevent a malfunction caused by the substrate noise in a semiconductor device including an SOI substrate provided with the guard ring. Then, there is provided a semiconductor device, including: an SOI substrate in which a support substrate 10, an insulating layer 11, and an SOI layer 12 are stacked one by one; an element section 4 provided in one region of the SOI substrate; and a guard ring region 8 provided around the element section 4 of the SOI substrate, wherein a first diffusion layer 15 provided in the SOI layer 12 of the element section 4, and a second diffusion layer 26 provided in the SOI layer 12 of the guard ring region 8 are electrically connected to each other.
摘要翻译：本发明的目的是增加保护环中吸收的衬底噪声的量，并且防止包括设置有保护环的SOI衬底的半导体器件中的衬底噪声引起的故障。然后，提供一种半导体器件，包括：SOI衬底，其中支撑衬底10，绝缘层11和SOI层12一个一个地堆叠; 设置在SOI衬底的一个区域中的元件部分4; 以及设置在SOI衬底的元件部分4周围的保护环区域8，其中设置在元件部分4的SOI层12中的第一扩散层15和设置在护罩的SOI层12中的第二扩散层26 环形区域8彼此电连接。

7. 发明授权

US07256456B2 SOI substrate and semiconductor integrated circuit device 失效
标题翻译： SOI衬底和半导体集成电路器件
公开(公告)号：US07256456B2
公开(公告)日：2007-08-14
申请号：US10739166
申请日：2003-12-19
申请人： Hiroaki Ohkubo , Masayuki Furumiya , Ryota Yamamoto , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Masayuki Furumiya , Ryota Yamamoto , Yasutaka Nakashiba
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/743 , H01L21/84 , H01L27/1203
摘要： A semiconductor IC device includes a base substrate comprising P−-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and the N+-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N+-type silicon layer and the second P+-type silicon layer. The first P+-type silicon layer is connected to ground potential wiring GND, and the N+-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P+-type silicon layer and the N+-type silicon layer.
摘要翻译：半导体IC器件包括基底衬底，其包括P型 - 硅，第一P + +型硅层设置在基底衬底上，并且N + +型硅层和第二P + +型硅层设置在其上的同一层中。第一P + + / - 型硅层和N + + - 型硅层的杂质浓度高于基底衬底的杂质浓度。此外，在N + +型硅层和第二P + +型硅层的整个上表面上设置掩埋氧化物层和SOI层。第一P + + / - 型硅层连接到地电位布线GND，并且N + +型硅层连接到电源电位布线VDD。因此，在P + +型硅层和N + +型硅层之间形成与电源并联连接的去耦电容器。

8. 发明申请

US20060197127A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060197127A1
公开(公告)日：2006-09-07
申请号：US11362132
申请日：2006-02-27
申请人： Ryota Yamamoto , Yutaka Akiyama , Masayuki Furumiya
发明人： Ryota Yamamoto , Yutaka Akiyama , Masayuki Furumiya
IPC分类号： H01L31/113
CPC分类号： H01L21/84 , H01L21/761 , H01L21/76251 , H01L21/765 , H01L27/1203
摘要： An object is to increase the amount of substrate noise absorbed in a guard ring, and to prevent a malfunction caused by the substrate noise in a semiconductor device including an SOI substrate provided with the guard ring. Then, there is provided a semiconductor device, including: an SOI substrate in which a support substrate 10, an insulating layer 11, and an SOI layer 12 are stacked one by one; an element section 4 provided in one region of the SOI substrate; and a guard ring region 8 provided around the element section 4 of the SOI substrate, wherein a first diffusion layer 15 provided in the SOI layer 12 of the element section 4, and a second diffusion layer 26 provided in the SOI layer 12 of the guard ring region 8 are electrically connected to each other.
摘要翻译：本发明的目的是增加保护环中吸收的衬底噪声的量，并且防止包括设置有保护环的SOI衬底的半导体器件中的衬底噪声引起的故障。然后，提供一种半导体器件，包括：SOI衬底，其中支撑衬底10，绝缘层11和SOI层12一个一个地堆叠; 设置在SOI衬底的一个区域中的元件部分4; 以及设置在SOI衬底的元件部分4周围的保护环区域8，其中设置在元件部分4的SOI层12中的第一扩散层15和设置在护罩的SOI层12中的第二扩散层26 环形区域8彼此电连接。

9. 发明申请

US20050134419A1 Semiconductor integrated circuit and fabrication method thereof 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US20050134419A1
公开(公告)日：2005-06-23
申请号：US11017074
申请日：2004-12-21
申请人： Masayuki Furumiya , Ryota Yamamoto
发明人： Masayuki Furumiya , Ryota Yamamoto
IPC分类号： H01F41/04 , H01F17/00 , H01F17/04 , H01L21/02 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/04 , H01F5/00
CPC分类号： H01L28/10 , H01F17/0006 , H01F41/046 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A multilayer interconnection layer is provided on a semiconductor substrate. An inductor is provided on an insulating layer that forms the uppermost layer of the multilayer interconnection layer. The inductor is formed by spirally arranging a single wiring. On the insulating layer, a multilayer structure body is provided in an inner region of the inductor. In the multilayer structure body, a plurality of ferromagnetic cores formed of Ni are arranged in a matrix. The height of each ferromagnetic core is equal to or larger than the width thereof.
摘要翻译：多层互连层设置在半导体衬底上。电感器设置在形成多层互连层的最上层的绝缘层上。电感器通过螺旋地布置单个布线而形成。在绝缘层上，在电感器的内部区域设置多层结构体。在多层结构体中，由Ni构成的多个铁磁性核排列成矩阵状。每个铁磁芯的高度等于或大于其宽度。

10. 发明申请

US20060231923A1 Inductor for semiconductor integrated circuit and method of fabricating the same 审中-公开
公开(公告)号：US20060231923A1
公开(公告)日：2006-10-19
申请号：US11455678
申请日：2006-06-20
申请人： Ryota Yamamoto , Masayuki Furumiya , Hiraoki Ohkubo , Yasutaka Nakashiba
发明人： Ryota Yamamoto , Masayuki Furumiya , Hiraoki Ohkubo , Yasutaka Nakashiba
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L28/10 , H01L21/76838 , H01L23/5227 , H01L23/53228 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are an inductor for a semiconductor integrated circuit, which provides a wider cross-sectional area, significantly reduces the resistance to improve the Q value and has a highly uniform film thickness, and a method of fabricating the inductor. A spiral inductor is formed on a topmost interconnection layer of a multilayer interconnection layer formed by a damascene method. This inductor is formed by patterning a barrier metal layer on an insulation film, on which a topmost interconnection is formed, in such a way that the barrier metal layer contacts the topmost interconnection, then forming a protective insulation film on an entire surface of the barrier metal layer, forming an opening in that portion of the protective insulation film which lies over the barrier metal layer, forming a thick Cu film with the barrier metal layer serving as a plating electrode, and performing wet etching of the Cu film. This process can allow the inductor to be so formed as to be thick and have a wide line width.

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