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1. 发明授权

US07986026B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US07986026B2
公开(公告)日：2011-07-26
申请号：US12707121
申请日：2010-02-17
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

2. 发明授权

US07663207B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07663207B2
公开(公告)日：2010-02-16
申请号：US11407323
申请日：2006-04-20
申请人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
发明人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.
摘要翻译：半导体器件包括具有MIM结构的电容器，通过该电容器提高器件的尺寸精度，并给出稳定的电容值。半导体器件100包括：半导体衬底102; 形成有MIM电容器的电容器形成区域130，其具有形成在半导体衬底102上的绝缘中间层104，第一电极110和第二电极112，并且第一电极110和第二电极112面向彼此通过绝缘夹层104; 以及屏蔽区域132，其包括形成在电容器形成区域130的外边缘中的多个屏蔽电极114，并且同时在与半导体衬底上的MIM电容器相同的层中设定预定电位 102，并且将电容器形成区域130与其他区域屏蔽。

3. 发明申请

US20060087004A1 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
公开(公告)号：US20060087004A1
公开(公告)日：2006-04-27
申请号：US11247296
申请日：2005-10-12
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

4. 发明授权

US08378454B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US08378454B2
公开(公告)日：2013-02-19
申请号：US13173709
申请日：2011-06-30
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

5. 发明授权

US07432170B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07432170B2
公开(公告)日：2008-10-07
申请号：US11017695
申请日：2004-12-22
申请人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
摘要翻译：在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便形成下电极和下布线。以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。

6. 发明授权

US07705422B2 Semiconductor device including metal-insulator-metal capacitor arrangement 失效
标题翻译：半导体器件包括金属 - 绝缘体 - 金属电容器布置
公开(公告)号：US07705422B2
公开(公告)日：2010-04-27
申请号：US11247296
申请日：2005-10-12
申请人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
发明人： Masayuki Furumiya , Kuniko Kikuta , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.
摘要翻译：半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

7. 发明申请

US20060237819A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060237819A1
公开(公告)日：2006-10-26
申请号：US11407323
申请日：2006-04-20
申请人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
发明人： Kuniko Kikuta , Masayuki Furumiya , Ryota Yamamoto , Makoto Nakayama
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.
摘要翻译：半导体器件包括具有MIM结构的电容器，通过该电容器提高器件的尺寸精度，并给出稳定的电容值。半导体器件100包括：半导体衬底102; 形成有MIM电容器的电容器形成区域130，其具有形成在半导体衬底102上的绝缘中间层104，第一电极110和第二电极112，并且第一电极110和第二电极112面向彼此通过绝缘夹层104; 以及屏蔽区域132，其包括形成在电容器形成区域130的外边缘中的多个屏蔽电极114，并且同时在与半导体衬底上的MIM电容器相同的层中设定预定电位 102，并且将电容器形成区域130与其他区域屏蔽。

8. 发明申请

US20050139956A1 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20050139956A1
公开(公告)日：2005-06-30
申请号：US11017695
申请日：2004-12-22
申请人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
发明人： Hiroaki Ohkubo , Ryota Yamamoto , Masayuki Furumiya , Masaharu Sato , Kuniko Kikuta , Makoto Nakayama , Yasutaka Nakashiba
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L23/522 , H01L21/8234 , H01L21/20 , H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.
摘要翻译：在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便形成下电极和下布线。以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。

9. 发明授权

US07414506B2 Semiconductor integrated circuit and fabrication method thereof 失效
标题翻译：半导体集成电路及其制作方法
公开(公告)号：US07414506B2
公开(公告)日：2008-08-19
申请号：US11017074
申请日：2004-12-21
申请人： Masayuki Furumiya , Ryota Yamamoto
发明人： Masayuki Furumiya , Ryota Yamamoto
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01F17/0006 , H01F41/046 , H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A multilayer interconnection layer is provided on a semiconductor substrate. An inductor is provided on an insulating layer that forms the uppermost layer of the multilayer interconnection layer. The inductor is formed by spirally arranging a single wiring. On the insulating layer, a multilayer structure body is provided in an inner region of the inductor. In the multilayer structure body, a plurality of ferromagnetic cores formed of Ni are arranged in a matrix. The height of each ferromagnetic core is equal to or larger than the width thereof.
摘要翻译：多层互连层设置在半导体衬底上。电感器设置在形成多层互连层的最上层的绝缘层上。电感器通过螺旋地布置单个布线而形成。在绝缘层上，在电感器的内部区域设置多层结构体。在多层结构体中，由Ni构成的多个铁磁性核排列成矩阵状。每个铁磁芯的高度等于或大于其宽度。

10. 发明授权

US07053165B2 Semiconductor integrated circuit including an inductor and method of manufacturing the same 有权
标题翻译：包括电感器的半导体集成电路及其制造方法
公开(公告)号：US07053165B2
公开(公告)日：2006-05-30
申请号：US10600104
申请日：2003-06-20
申请人： Masayuki Furumiya , Ryota Yamamoto
发明人： Masayuki Furumiya , Ryota Yamamoto
IPC分类号： H01L29/00
CPC分类号： H01L28/10 , H01F17/0006 , H01F27/34 , H01F41/046 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device, and method of manufacturing the same, includes an inductor with improved inductance and an improved quality factor (Q-factor) that can be miniaturized. In one example, an inductor (3) is provided on an insulating layer (2) of a multilayer interconnection layer (1). The inductor (3) is formed by a spiral arrangement of a wiring (3a). A lamination film (14) is provided in an internal region (13) of an inductor (3) on insulating layer (2), and can be formed by laminating a titanium-tungsten (TiW) layer (9), a copper (Cu) layer (10), a ferromagnetic substance layer (15) made of nickel (Ni), a Cu layer (11), and a TiW layer (12), in that order. A lower surface of ferromagnetic substance layer (15) can be lower than an upper surface of wiring layer (3a), and an upper surface of ferromagnetic substance layer (15) can be higher than a lower surface of wiring layer (3a). As a result, a lower portion of ferromagnetic substance layer (15) can be at the same layer (level) as wiring layer (3a). An upper surface of lamination film (14) can be made higher than a wiring layer (3a), and a lower surface of lamination film (14) can be made lower than a lower surface of a wiring layer (3a).
摘要翻译：半导体集成电路器件及其制造方法包括具有改善的电感的电感器和可以小型化的改进的品质因数（Q因子）。在一个示例中，电感器（3）设置在多层互连层（1）的绝缘层（2）上。电感器（3）由布线（3a）的螺旋布置形成。层叠膜（14）设置在绝缘层（2）上的电感器（3）的内部区域（13）中，并且可以通过层压钛 - 钨（TiW）层（9），铜（Cu ）层（10），由镍（Ni）制成的铁磁物质层（15），Cu层（11）和TiW层（12）。铁磁物质层（15）的下表面可以比布线层（3a）的上表面低，并且铁磁物质层（15）的上表面可以高于布线层（3a）的下表面，。结果，铁磁物质层（15）的下部可以与布线层（3a）处于相同的层（层）。层叠膜（14）的上表面可以比布线层（3a）高，并且层压膜（14）的下表面可以被制成低于布线层（3a）的下表面。

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