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1. 发明授权

US06731293B2 Image output device and image output control method 失效
标题翻译：图像输出设备和图像输出控制方式
公开(公告)号：US06731293B2
公开(公告)日：2004-05-04
申请号：US09867708
申请日：2001-05-31
申请人： Masayoshi Tojima , Toshihiro Moriiwa , Masatoshi Matsuo
发明人： Masayoshi Tojima , Toshihiro Moriiwa , Masatoshi Matsuo
IPC分类号： G06F1300
CPC分类号： G09G5/393 , G09G5/18 , G09G5/397 , G09G2340/0407
摘要： The present invention provides an image output device which can periodically update display of image data as well as update the display images immediately and with minimum data transfer. A data transfer request control circuit 107 including a frame rate register 108 for deciding a data transfer request issue cycle and a data transfer request issuing unit 109 is provided in a video processing unit 104 of the image output device. When an update flag is set in the frame rate register 108, the data transfer request is issued in the next transfer section, regardless of the periodic transfer cycle, and the image data stored in the frame memory 106 are update.
摘要翻译：本发明提供一种可以周期性地更新图像数据的显示以及立即更新显示图像并且以最小的数据传送的图像输出装置。包括用于决定数据传送请求发布周期的帧速率寄存器108和数据传送请求发布单元109的数据传送请求控制电路107被提供在图像输出设备的视频处理单元104中。当在帧速率寄存器108中设置更新标志时，无论周期性传送周期如何，都在下一个传送部分中发出数据传送请求，并且更新存储在帧存储器106中的图像数据。

2. 发明授权

US07038737B1 Image processing device 失效
标题翻译：图像处理装置
公开(公告)号：US07038737B1
公开(公告)日：2006-05-02
申请号：US09856634
申请日：1999-11-25
申请人： Yasuo Kohashi , Toshihiro Moriiwa , Masayoshi Tojima , Shunichi Kuromaru , Masahiro Oohashi
发明人： Yasuo Kohashi , Toshihiro Moriiwa , Masayoshi Tojima , Shunichi Kuromaru , Masahiro Oohashi
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The image processing apparatus according to the present invention comprises: DMA control means 112 having image input/output processing means 100, an external memory 111, DMA setting holding means 113, address generating means 114, DRAM control means 115, DMA request generating means 119, and DMA request adjusting means 120; a processor 116 including encoding/decoding processing means 117; and a DMA bus 118 as shown in FIG. 1. In the image processing apparatus so constructed, a transfer data group which can be previously subjected to DMA scheduling is divided into burst transfer units, and the DMA request generating means periodically issues the DMA request in the burst transfer units and performs DMA of the transfer data which cannot be subjected to the DMA scheduling during the period that the DMA of the transfer data is not performed, thereby avoiding concentration of specific DMA.
摘要翻译：根据本发明的图像处理装置包括：具有图像输入/输出处理装置100，外部存储器111，DMA设置保持装置113，地址生成装置114，DRAM控制装置115，DMA请求生成装置119的DMA控制装置112 ，和DMA请求调整装置120; 包括编码/解码处理装置117的处理器116; 和DMA总线118，如图1所示。在这样构成的图像处理装置中，将可以预先进行DMA调度的传送数据组划分为突发传送单元，DMA请求生成单元在突发传送单元中周期性地发出DMA请求，并执行DMA 在不执行传输数据的DMA的时段内传送不能进行DMA调度的数据，从而避免特定DMA的集中。

3. 发明授权

US08406308B2 Encoding apparatus for encoding binary signals generated from binarized multivalued syntax elements and method for performing the same 有权
标题翻译：用于编码由二值化多值语法元素生成的二进制信号的编码装置及其执行方法
公开(公告)号：US08406308B2
公开(公告)日：2013-03-26
申请号：US12761493
申请日：2010-04-16
申请人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
发明人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
IPC分类号： H04N7/32
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： An encoding device encoding binary signals using arithmetic-encoding. The encoding device includes a binarization unit binarizing multivalued syntax elements in order to generate the binary signals. The generated binary signals are stored on an intermediate buffer. Further, the encoding device includes an arithmetic-encoding unit performing the arithmetic-encoding on the binary signals stored on the intermediate buffer. Additionally, the generated binary signals are binary representations of values of the multivalued syntax elements.
摘要翻译：使用算术编码对二进制信号进行编码的编码装置。编码装置包括二值化单元，二值化多值语法元素以便生成二进制信号。生成的二进制信号存储在中间缓冲器上。此外，编码装置包括对存储在中间缓冲器上的二进制信号执行算术编码的算术编码单元。另外，生成的二进制信号是多值语法元素的值的二进制表示。

4. 发明申请

US20060161877A1 Device and method for data-processing 审中-公开
标题翻译：用于数据处理的设备和方法
公开(公告)号：US20060161877A1
公开(公告)日：2006-07-20
申请号：US11289442
申请日：2005-11-30
申请人： Mana Hamada , Masayoshi Tojima , Koji Kai , Tsuyoshi Nakamura , Akihiko Inoue
发明人： Mana Hamada , Masayoshi Tojima , Koji Kai , Tsuyoshi Nakamura , Akihiko Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/86
摘要： A total specification is divided into a hardware specification and a software specification. With respect to the hardware specification, a first hardware description is described. With respect to the software specification, an object program is generated, which is converted into a second hardware description. The first and second hardware descriptions are logically synthesized into a net list, which includes a part that fulfills the software specification. Since the object program is converted into the second hardware description, which is logically synthesized, the redundancy of the program can be removed and cost for manufacturing hardware can be reduced.
摘要翻译：总规范分为硬件规格和软件规范。关于硬件规范，描述了第一硬件描述。关于软件规范，生成对象程序，将其转换为第二硬件描述。第一和第二硬件描述在逻辑上合成为一个网络列表，其中包括满足软件规范的部分。由于将对象程序转换成逻辑合成的第二硬件描述，所以可以消除程序的冗余，并且可以降低制造硬件的成本。

5. 发明授权

US07062728B2 Method of designing a logic circuit utilizing an algorithm based in C language 失效
标题翻译：使用基于C语言的算法设计逻辑电路的方法
公开(公告)号：US07062728B2
公开(公告)日：2006-06-13
申请号：US10167579
申请日：2002-06-13
申请人： Masayoshi Tojima
发明人： Masayoshi Tojima
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An algorithm C description describing an algorithm of computation or control of a logic circuit in a C language is split into a plurality of states in units of processing, and the execution order of the split processing is described as state transition, to generate a functional C description with a control description embedded therein. A clock description as the conception of time is inserted in the functional C description, to be converted into a RT level C description. The RT level C description is converted into a RT level description in HDL with an existing conversion tool.
摘要翻译：将描述C语言中的逻辑电路的计算或控制算法的算法C描述以处理为单位划分为多个状态，将分割处理的执行顺序描述为状态转换，以生成功能C 具有嵌入其中的控制描述的描述。作为时间概念的时钟描述被插入到功能C描述中，以被转换成RT级别C描述。使用现有的转换工具，将RT级别C描述转换为HDL中的RT级别描述。

6. 发明授权

US06853589B2 Clock phase adjustment method, integrated circuit, and method for designing the integrated circuit 失效
标题翻译：时钟相位调整方法，集成电路及集成电路设计方法
公开(公告)号：US06853589B2
公开(公告)日：2005-02-08
申请号：US10383611
申请日：2003-03-10
申请人： Masayoshi Tojima , Hiromasa Nakajima , Masahiro Oohashi , Yasuo Kohashi
发明人： Masayoshi Tojima , Hiromasa Nakajima , Masahiro Oohashi , Yasuo Kohashi
IPC分类号： G06F1/10 , G06F17/50 , G11C7/10 , G11C7/22 , G11C7/00 , G11C8/00
CPC分类号： G11C7/222 , G06F1/10 , G06F17/5045 , G11C7/1072 , G11C7/22
摘要： The time required for access to a SDRAM (110) is extracted from the layout of an integrated circuit (1000), a first phase difference between an external clock SDCLKO and an internal clock ICLK is calculated, and the value of delay of the external clock signal or the internal clock signal in the integrated circuit (1000) is changed on the basis of the calculated first phase difference, whereby clock phase adjustment for the integrated circuit (1000) in the designing stage is realized.
摘要翻译：从集成电路（1000）的布局中提取访问SDRAM（110）所需的时间，计算外部时钟SDCLKO和内部时钟ICLK之间的第一相位差，并且外部时钟的延迟值基于计算出的第一相位差来改变集成电路（1000）中的信号或内部时钟信号，由此实现设计阶段中的集成电路（1000）的时钟相位调整。

7. 发明授权

US08120675B2 Moving image recording/playback device 有权
标题翻译：运动图像录制/播放设备
公开(公告)号：US08120675B2
公开(公告)日：2012-02-21
申请号：US11907692
申请日：2007-10-16
申请人： Masayoshi Tojima
发明人： Masayoshi Tojima
IPC分类号： H04N5/92
CPC分类号： H04N5/772 , H04N5/907 , H04N9/7921 , H04N9/8042 , H04N9/8045 , H04N21/234327 , H04N21/4223 , H04N21/4325 , H04N21/4334 , H04N21/440254 , H04N21/440263 , H04N21/8455 , H04N21/8456
摘要： A moving image recording/playback device records a moving image of a subject. In the case of recording, the moving image recording/playback device sequentially outputs a plurality of image frames that constitute the moving image at a predetermined frame rate and, for the plurality of image frames, records whole image frames at intervals of a predetermined number of frames and partly records other image frames, onto at least one recording medium. In the case of playback, when reading a partly recorded image frame, the moving image recording/playback device generates a display frame from the partly recorded image frame and a recorded whole image frame.
摘要翻译：运动图像记录/重放装置记录被摄体的运动图像。在记录的情况下，运动图像记录/重放装置以预定的帧速顺序地输出构成运动图像的多个图像帧，并且对于多个图像帧，以预定数量的间隔记录整个图像帧帧并部分地将其他图像帧记录到至少一个记录介质上。在回放的情况下，当读取部分记录的图像帧时，运动图像记录/重放装置从部分记录的图像帧和记录的整个图像帧生成显示帧。

8. 发明申请

US20070192565A1 Semiconductor device and mobile phone using the same 审中-公开
标题翻译：半导体器件和手机使用相同
公开(公告)号：US20070192565A1
公开(公告)日：2007-08-16
申请号：US10575784
申请日：2005-03-28
申请人： Masashi Hoshino , Masayoshi Tojima , Youichi Nishida
发明人： Masashi Hoshino , Masayoshi Tojima , Youichi Nishida
IPC分类号： G06F15/00
CPC分类号： G06F15/7832
摘要： A semiconductor device (100) comprises a processor unit (110) including an internal CPU (113), an internal interface section (130), an external interface section (140) including an interface unit (143) connected to an external CPU (201), a plurality of processing circuits (121)-(126), and a connection control circuit (180). The internal interface section (130) includes a first bus (191) connected to the internal CPU (113), a second bus (192) connected to the external CPU (201) through the interface unit (143), and selecting circuits (131)-(136), controlled by the connection control circuit (180) according to the instruction of the internal CPU (113) or the external CPU (201), and operable to select respective connections of the plurality of processing circuits (121)-(126) to the first bus (191) or to the second bus (192). All the processing circuits (121)-(126) are controllable by the internal CPU (113) and the external CPU (201).
摘要翻译：一种半导体器件（100），包括：处理器单元（110），包括内部CPU（113），内部接口部分（130），外部接口部分（140），其包括连接到外部CPU（201）的接口单元），多个处理电路（121） - （126）和连接控制电路（180）。内部接口部分（130）包括连接到内部CPU（113）的第一总线（191），通过接口单元（143）连接到外部CPU（201）的第二总线（192），以及选择电路） - （136），由连接控制电路（180）根据内部CPU（113）或外部CPU（201）的指令控制，并且可操作以选择多个处理电路（121）的各个连接 - （126）连接到第一总线（191）或第二总线（192）。所有处理电路（121） - （126）都可由内部CPU（113）和外部CPU（201）控制。

9. 发明申请

US20070043886A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070043886A1
公开(公告)日：2007-02-22
申请号：US11589840
申请日：2006-10-31
申请人： Masayoshi Tojima , Hiroshi Miyajima , Yoshinori Okajima
发明人： Masayoshi Tojima , Hiroshi Miyajima , Yoshinori Okajima
IPC分类号： G06F13/28
CPC分类号： G06F12/0692 , G06F15/7857
摘要： A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.
摘要翻译：半导体集成电路装置包括多个内部存储器，构成具有编解码功能的第一处理单元的主处理器，以及构成用于视频显示处理的第二处理单元的视频接口和图形处理器。半导体集成电路器件在连接到作为外部处理单元的CPU和外部存储器时工作。半导体集成电路装置具有存储器配置控制器，用于根据应用控制对第一，第二和外部处理单元的存储器分配。

10. 发明授权

US06647539B1 Method of designing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件设计方法
公开(公告)号：US06647539B1
公开(公告)日：2003-11-11
申请号：US09710910
申请日：2000-11-14
申请人： Masayoshi Tojima , Masahiro Ohashi , Mana Hamada , Miki Arita , Yuji Sugisawa
发明人： Masayoshi Tojima , Masahiro Ohashi , Mana Hamada , Miki Arita , Yuji Sugisawa
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A system which allows signal transmission between circuit locks is constructed promptly by automatically generating an I/F circuit in response to the adjustment of a timing relationship and to a modification in a waveform on a GUI and automatically inserting the I/F circuit between the circuit blocks or adding the I/F circuit to any of the circuit block. A circuit for outputting an operation enable for a receiving side is generated automatically between a plurality of blocks operating with different frequencies, whereby the use of the circuit blocks is expanded in spite of the different frequencies. Further, the design of a large-scale system is performed efficiently by automatically generating a desired waveform by a simple editing operation, generating a desired signal waveform by forming a combinational circuit of signals in the circuit block, and automatically generating a logic synthesis script.
摘要翻译：通过自动产生I / F电路来响应于时序关系的调整和GUI上的波形的修改，迅速地构成允许电路锁之间的信号传输的系统，并且自动地将I / F电路插入电路块或将I / F电路添加到任何电路块。用于输出用于接收侧的操作使能的电路在以不同频率操作的多个块之间自动生成，由此尽管频率不同，电路块的使用也被扩展。此外，通过简单的编辑操作自动生成期望的波形，通过形成电路块中的信号的组合电路，生成期望的信号波形，自动生成逻辑综合脚本，有效地执行大规模系统的设计。

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