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1. 发明授权

US06629230B2 Host interface circuit 失效
公开(公告)号：US06629230B2
公开(公告)日：2003-09-30
申请号：US09871144
申请日：2001-05-30
申请人： Takashi Hashimoto , Yasuo Kohashi
发明人： Takashi Hashimoto , Yasuo Kohashi
IPC分类号： G06F1200
CPC分类号： G06F13/387 , G06F13/1631 , Y02D10/14 , Y02D10/151
摘要： In a host interface circuit performing data transmission/reception between an external host controller and a device connected to the external host controller, the external host controller generates, as external addresses to be supplied to the connected device, first addresses corresponding to the respective internal addresses in an internal storage space of the connected device, and a specific second address corresponding to internal addresses of a series of areas in the internal storage space; and the host interface circuit includes a first address conversion circuit for converting the first addresses into the internal addresses in the internal storage space, and a second address conversion circuit for converting the specific second address into the internal addresses in the internal storage space; and the specific second address is used when the external host controller makes continuous access to the serial areas in the internal storage space of the connected device. Therefore, the external host controller can make continuous access to a series of areas in the internal storage space of the connected device by using the specific address, without using DMA, between the external host controller and the host interface circuit. As the result, power consumption is reduced, and complexity in software processing is reduced.

2. 发明授权

US07197581B2 Integrated circuit, device and method for inputting/outputting images 失效
标题翻译：用于输入/输出图像的集成电路，装置和方法
公开(公告)号：US07197581B2
公开(公告)日：2007-03-27
申请号：US10821931
申请日：2004-04-12
申请人： Yasuo Kohashi
发明人： Yasuo Kohashi
IPC分类号： G06F13/28 , G06F13/14 , G06F13/36
CPC分类号： G06F13/28
摘要： The integrated circuit comprises, in addition to a first bus and a first DMA controller, a second bus and a second DMA controller that mutually connects the first bus and the second bus. A main memory is connected to the first bus, and a frame memory is connected to the second bus.By the construction, a possible conflict in data transfer as “urgent processing” and as “normal processing” can be avoided. The data transfer as “urgent processing” includes transferring image data between the frame memory and an image input device or an image display device; while the data transfer as “normal processing” includes transferring image data between the main memory and the frame memory.
摘要翻译：除了第一总线和第一DMA控制器之外，集成电路还包括相互连接第一总线和第二总线的第二总线和第二DMA控制器。主存储器连接到第一总线，并且帧存储器连接到第二总线。

3. 发明授权

US08433149B2 Image transmitter and image receiver, for transmitting/receiving image data to/from a device connected by a signal data line 失效
标题翻译：图像发送器和图像接收器，用于向/从通过信号数据线连接的设备发送/接收图像数据
公开(公告)号：US08433149B2
公开(公告)日：2013-04-30
申请号：US13129004
申请日：2009-11-13
申请人： Yoshiteru Tanaka , Yasuo Kohashi , Toshiyuki Ishioka
发明人： Yoshiteru Tanaka , Yasuo Kohashi , Toshiyuki Ishioka
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： G06F3/14
摘要： A system LSI serving as an image transmitter is a device for transmitting image data to a display device LCD connected by a data signal line. The system LSI comprises: an output image memory for storing the image data to be transmitted; a subtraction processing unit for reading the image data from the output image memory and obtaining the data of the difference between mutually adjacent pixels of the image data; and a data transmission unit for sequentially outputting a data signal, which expresses the difference data corresponding to the pixels as a binary number, to the data signal line in accordance with the arrangement of the pixels; wherein the data signal of the difference data in which the number of signal changes is reduced more than the case of outputting the pixel data to the data signal line is output.
摘要翻译：用作图像发送器的系统LSI是用于将图像数据发送到由数据信号线连接的显示装置LCD的装置。系统LSI包括：输出图像存储器，用于存储要发送的图像数据; 减法处理单元，用于从输出图像存储器读取图像数据，并获得图像数据的相邻像素之间的差异的数据; 以及数据发送单元，用于根据像素的配置顺序地将表示与二进制数的像素对应的差分数据的数据信号输出到数据信号线; 其中输出比将数据输出到数据信号线的情况更多地减少信号变化次数的差分数据的数据信号。

4. 发明授权

US06853589B2 Clock phase adjustment method, integrated circuit, and method for designing the integrated circuit 失效
标题翻译：时钟相位调整方法，集成电路及集成电路设计方法
公开(公告)号：US06853589B2
公开(公告)日：2005-02-08
申请号：US10383611
申请日：2003-03-10
申请人： Masayoshi Tojima , Hiromasa Nakajima , Masahiro Oohashi , Yasuo Kohashi
发明人： Masayoshi Tojima , Hiromasa Nakajima , Masahiro Oohashi , Yasuo Kohashi
IPC分类号： G06F1/10 , G06F17/50 , G11C7/10 , G11C7/22 , G11C7/00 , G11C8/00
CPC分类号： G11C7/222 , G06F1/10 , G06F17/5045 , G11C7/1072 , G11C7/22
摘要： The time required for access to a SDRAM (110) is extracted from the layout of an integrated circuit (1000), a first phase difference between an external clock SDCLKO and an internal clock ICLK is calculated, and the value of delay of the external clock signal or the internal clock signal in the integrated circuit (1000) is changed on the basis of the calculated first phase difference, whereby clock phase adjustment for the integrated circuit (1000) in the designing stage is realized.
摘要翻译：从集成电路（1000）的布局中提取访问SDRAM（110）所需的时间，计算外部时钟SDCLKO和内部时钟ICLK之间的第一相位差，并且外部时钟的延迟值基于计算出的第一相位差来改变集成电路（1000）中的信号或内部时钟信号，由此实现设计阶段中的集成电路（1000）的时钟相位调整。

5. 发明授权

US06791625B1 Video processing apparatus for performing address generation and control, and method therefor 失效
标题翻译：用于执行地址产生和控制的视频处理装置及其方法
公开(公告)号：US06791625B1
公开(公告)日：2004-09-14
申请号：US09868183
申请日：2001-07-12
申请人： Yasuo Kohashi , Toshihiro Moriiwa , Shunichi Kuromaru , Hiromasa Nakajima , Tomonori Yonezawa , Miki Arita
发明人： Yasuo Kohashi , Toshihiro Moriiwa , Shunichi Kuromaru , Hiromasa Nakajima , Tomonori Yonezawa , Miki Arita
IPC分类号： H04N964
CPC分类号： H04N19/43 , H04N19/423 , H04N19/51 , H04N19/61
摘要： Apparatus and method for data transmission while performing encoding processing on a non-limited moving vector mode, which avoids an increase in required memory capacity and a reduction in processing load, the apparatus comprising a two dimensional address generating unit for generating an access address of an external memory and an address control unit for administrating the horizontal position and the vertical position of the extended logical space and generating an operation authorizing signal for the two dimensional address generating unit, and the two dimensional address generating unit and the address control unit are operated in relation to each other so that an access address to outside the effective video data region is controlled to be an address of a pixel data at the periphery of the effective video data region, thereby reducing the extended region in the external memory.
摘要翻译：在对非限制的移动矢量模式进行编码处理时进行数据传输的装置和方法，其避免所需存储器容量的增加和处理负载的减少，所述装置包括二维地址生成单元，用于生成外部存储器和用于管理扩展逻辑空间的水平位置和垂直位置的地址控制单元，并且生成用于二维地址生成单元的操作授权信号，并且二维地址生成单元和地址控制单元在使得有效视频数据区域之外的访问地址被控制为有效视频数据区域的周边处的像素数据的地址，从而减少外部存储器中的扩展区域。

6. 发明授权

US5999654A Image processor capable of transferring image data from an input buffer to memory at a high rate of speed 失效
标题翻译：图像处理器能够以高速率将图像数据从输入缓冲器传送到存储器
公开(公告)号：US5999654A
公开(公告)日：1999-12-07
申请号：US895615
申请日：1997-07-16
申请人： Masayoshi Toujima , Yasuo Kohashi , Hitoshi Fujimoto , Tomonori Yonezawa , Masatoshi Matsuo , Shunichi Kurohmaru
发明人： Masayoshi Toujima , Yasuo Kohashi , Hitoshi Fujimoto , Tomonori Yonezawa , Masatoshi Matsuo , Shunichi Kurohmaru
IPC分类号： G06T1/60 , G06K9/36
CPC分类号： G06T1/60
摘要： A bus switch is connected among an input buffer memory, a data memory, and an encoding unit, to select between a first bus connection of the input buffer memory and the data memory and a second bus connection of the data memory and the encoding unit. A data transfer control unit controls the bus switch to select the first bus connection in response to a data request signal from the encoding unit, controls the process of reading from the input buffer memory and the process of writing into the data memory, controls the bus switch to select the second bus connection upon completion of the transfer of one unit of image data, and sends a transfer completion signal in order of causing the encoding unit to start performing encoding processing. This makes it possible to transfer image data from the input buffer memory to the data memory at high speed.
摘要翻译：在输入缓冲存储器，数据存储器和编码单元之间连接总线开关，以在输入缓冲存储器的第一总线连接和数据存储器之间选择数据存储器和编码单元的第二总线连接。数据传输控制单元响应于来自编码单元的数据请求信号控制总线开关选择第一总线连接，控制从输入缓冲存储器读取的处理和写入数据存储器的处理，控制总线切换到在完成一个单位图像数据的传送时选择第二总线连接，并且按照编码单元开始执行编码处理的顺序发送传送完成信号。这使得可以高速地将图像数据从输入缓冲存储器传送到数据存储器。

7. 发明授权

US5584202A Method and apparatus for manufacturing internal gear, internal gear structure and reduction mechanism unit having internal gear structure 失效
标题翻译：用于制造内齿轮，内齿轮结构和具有内齿轮结构的减速机构单元的方法和装置
公开(公告)号：US5584202A
公开(公告)日：1996-12-17
申请号：US294868
申请日：1994-08-29
申请人： Hisanobu Kanamaru , Yasuo Kohashi
发明人： Hisanobu Kanamaru , Yasuo Kohashi
IPC分类号： B21D53/28 , B21H5/02 , F02N15/02 , F16H55/17
CPC分类号： B21D53/28 , B21H5/025
摘要： A steel sheet material is stamped from a coil stock material to form a disc blank member. The disc blank member is pressed to form an ash tray metal member. The ash tray metal member is sized to form a hollow cylindric metal body having a flange portion, a cylindric porion and a bottom portion by a press working. The cylindric metal body is inserted a central porion of a mandrel having a tooth profile part. The cylindric metal body is clamped and held by a drive shaft and a driven shaft which are rotated together with the mandrel. Under this state, the cylindric portion of the cylindric metal body is pressed by a roller. The metal of the cylindric portion of the cylindric metal body is fluidized plastically along the tooth profile part of the mandrel, thereby an internal gear is formed on the cylindric portion. The internal gear is applied to a reduction gear mechanism starter for use in an automobile.
摘要翻译：钢板材由卷材原料冲压而形成盘坯件。盘片坯件被压制成灰托盘金属件。灰托盘金属构件的尺寸设计成通过冲压加工形成具有凸缘部分，圆柱形孔和底部的中空圆柱形金属体。圆柱形金属体插入具有齿形部分的心轴的中心部分。圆柱形金属体被驱动轴和从动轴夹持并与心轴一起旋转。在这种状态下，圆柱形金属体的圆柱形部分被一个辊压紧。圆柱形金属体的圆柱形部分的金属沿心轴的齿形部分流态化，从而在圆柱形部分上形成内齿轮。内齿轮被应用于用于汽车的减速机构起动器。

8. 发明授权

US06188440B1 Image processor 失效
标题翻译：图像处理器
公开(公告)号：US06188440B1
公开(公告)日：2001-02-13
申请号：US09090984
申请日：1998-06-05
申请人： Masayoshi Toujima , Hiromasa Nakajima , Yasuo Kohashi , Hitoshi Fujimoto , Misako Matsumoto
发明人： Masayoshi Toujima , Hiromasa Nakajima , Yasuo Kohashi , Hitoshi Fujimoto , Misako Matsumoto
IPC分类号： H04N714
CPC分类号： H04N21/643 , H04N7/148 , H04N19/152 , H04N19/423 , H04N19/50 , H04N19/61
摘要： A conversion unit having a bidirectional conversion function of converting analog video signals into digital image data and vice versa and a processing unit having a function of encoding image data and of decoding encoded data are provided. A data transmission control unit switches the flow direction of each of image data and encoded data in response to an encoder/decoder switch signal. A process control unit performs switching of the receiving/transmitting of a control signal such as a transmission clock signal relating to encoded data in response to a master/slave set signal.
摘要翻译：一种具有将模拟视频信号转换为数字图像数据和反之亦然的双向转换功能的转换单元，以及具有编码图像数据和解码编码数据的功能的处理单元。数据传输控制单元响应于编码器/解码器切换信号切换图像数据和编码数据中的每一个的流向。处理控制单元响应于主/从设置信号执行诸如与编码数据相关的传输时钟信号的控制信号的接收/发送的切换。

9. 发明申请

US20110216980A1 IMAGE TRANSMITTER AND IMAGE RECEIVER 失效
标题翻译：图像发射器和图像接收器
公开(公告)号：US20110216980A1
公开(公告)日：2011-09-08
申请号：US13129004
申请日：2009-11-13
申请人： Yoshiteru Tanaka , Yasuo Kohashi , Toshiyuki Ishioka
发明人： Yoshiteru Tanaka , Yasuo Kohashi , Toshiyuki Ishioka
IPC分类号： G06K9/36
CPC分类号： G06F3/14
摘要： A system LSI serving as an image transmitter is a device for transmitting image data to a display device LCD connected by a data signal line. The system LSI comprises: an output image memory for storing the image data to be transmitted; a subtraction processing unit for reading the image data from the output image memory and obtaining the data of the difference between mutually adjacent pixels of the image data; and a data transmission unit for sequentially outputting a data signal, which expresses the difference data corresponding to the pixels as a binary number, to the data signal line in accordance with the arrangement of the pixels; wherein the data signal of the difference data in which the number of signal changes is reduced more than the case of outputting the pixel data to the data signal line is output.
摘要翻译：用作图像发送器的系统LSI是用于将图像数据发送到由数据信号线连接的显示装置LCD的装置。系统LSI包括：输出图像存储器，用于存储要发送的图像数据; 减法处理单元，用于从输出图像存储器读取图像数据，并获得图像数据的相邻像素之间的差异的数据; 以及数据发送单元，用于根据像素的配置顺序地将表示与二进制数的像素对应的差分数据的数据信号输出到数据信号线; 其中输出比将数据输出到数据信号线的情况更多地减少信号变化次数的差分数据的数据信号。

10. 发明授权

US07038737B1 Image processing device 失效
标题翻译：图像处理装置
公开(公告)号：US07038737B1
公开(公告)日：2006-05-02
申请号：US09856634
申请日：1999-11-25
申请人： Yasuo Kohashi , Toshihiro Moriiwa , Masayoshi Tojima , Shunichi Kuromaru , Masahiro Oohashi
发明人： Yasuo Kohashi , Toshihiro Moriiwa , Masayoshi Tojima , Shunichi Kuromaru , Masahiro Oohashi
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The image processing apparatus according to the present invention comprises: DMA control means 112 having image input/output processing means 100, an external memory 111, DMA setting holding means 113, address generating means 114, DRAM control means 115, DMA request generating means 119, and DMA request adjusting means 120; a processor 116 including encoding/decoding processing means 117; and a DMA bus 118 as shown in FIG. 1. In the image processing apparatus so constructed, a transfer data group which can be previously subjected to DMA scheduling is divided into burst transfer units, and the DMA request generating means periodically issues the DMA request in the burst transfer units and performs DMA of the transfer data which cannot be subjected to the DMA scheduling during the period that the DMA of the transfer data is not performed, thereby avoiding concentration of specific DMA.
摘要翻译：根据本发明的图像处理装置包括：具有图像输入/输出处理装置100，外部存储器111，DMA设置保持装置113，地址生成装置114，DRAM控制装置115，DMA请求生成装置119的DMA控制装置112 ，和DMA请求调整装置120; 包括编码/解码处理装置117的处理器116; 和DMA总线118，如图1所示。在这样构成的图像处理装置中，将可以预先进行DMA调度的传送数据组划分为突发传送单元，DMA请求生成单元在突发传送单元中周期性地发出DMA请求，并执行DMA 在不执行传输数据的DMA的时段内传送不能进行DMA调度的数据，从而避免特定DMA的集中。

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