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1. 发明授权

US06406958B2 Method of manufacturing nonvolatile semiconductor memory device 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US06406958B2
公开(公告)日：2002-06-18
申请号：US09819803
申请日：2001-03-29
申请人： Masataka Kato , Tetsuo Adachi , Hitoshi Kume , Shoji Shukuri
发明人： Masataka Kato , Tetsuo Adachi , Hitoshi Kume , Shoji Shukuri
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , Y10S257/90
摘要： A method of manufacturing a nonvolatile semiconductor memory device which is protected against deterioration in the electron injection/discharge characteristics between a floating gate of a memory cell and a channel. Three layers including a gate oxide film, a first polysilicon layer and a first nitride film are sequentially deposited on a silicon substrate surface and patterned with stripe-like columnwise lines. A second nitride film is formed on side walls of the columnwise lines, respectively. An element isolating insulation film is formed on the silicon substrate surface which is not covered with the first and second nitride films. After removal of the first and second nitride films, a first insulation film is formed on the side walls of the first polysilicon layer. Subsequently, at least two layers including a second insulation film and a second polysilicon layer are deposited and a pattern of rowwise lines extending orthogonally to the columnwise lines are formed by processing correspondingly the second polysilicon layer. Even after formation of the element isolating insulation film, thickening of the gate oxide film at distal portions thereof can be suppressed, whereby variations and deterioration in the characteristic of electron injection based on hot electron and tunnel phenomena can be minimized.
摘要翻译：一种制造非易失性半导体存储器件的方法，其被保护以防止存储单元的浮置栅极和沟道之间的电子注入/放电特性的劣化。在硅衬底表面上依次沉积包括栅极氧化膜，第一多晶硅层和第一氮化物膜的三个层，并用条纹状的列线进行图案化。分别在柱状线的侧壁上形成第二氮化物膜。在未被第一和第二氮化物膜覆盖的硅衬底表面上形成元件隔离绝缘膜。在去除第一和第二氮化物膜之后，在第一多晶硅层的侧壁上形成第一绝缘膜。随后，沉积包括第二绝缘膜和第二多晶硅层的至少两层，并且通过相应地处理第二多晶硅层来形成与柱状线垂直延伸的横线的图案。即使在形成元件隔离绝缘膜之后，也可以抑制其远端部分的栅极氧化膜的增厚，从而可以使基于热电子和隧道现象的电子注入特性的变化和劣化最小化。

2. 发明授权

US5932909A Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5932909A
公开(公告)日：1999-08-03
申请号：US851536
申请日：1997-05-05
申请人： Masataka Kato , Tetsuo Adachi , Hitoshi Kume , Shoji Shukuri
发明人： Masataka Kato , Tetsuo Adachi , Hitoshi Kume , Shoji Shukuri
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , Y10S257/90
摘要： A method of manufacturing a nonvolatile semiconductor memory device which is protected against deterioration in the electron injection/discharge characteristics between a floating gate of a memory cell and a channel. Three layers including a gate oxide film, a first polysilicon layer and a first nitride film are sequentially deposited on a silicon substrate surface and patterned with stripe-like columnwise lines. A second nitride film is formed on side walls of the columnwise lines, respectively. An element isolating insulation film is formed on the silicon substrate surface which is not covered with the first and second nitride films. After removal of the first and second nitride films, a first insulation film is formed on the side walls of the first polysilicon layer. Subsequently, at least two layers including a second insulation film and a second polysilicon layer are deposited and a pattern of rowwise lines extending orthogonally to the columnwise lines are formed by processing correspondingly the second polysilicon layer. Even after formation of the element isolating insulation film, thickening of the gate oxide film at distal portions thereof can be suppressed, whereby variations and deterioration in the characteristic of electron injection based on hot electron and tunnel phenomena can be minimized.
摘要翻译：一种制造非易失性半导体存储器件的方法，其被保护以防止存储单元的浮置栅极和沟道之间的电子注入/放电特性的劣化。在硅衬底表面上依次沉积包括栅极氧化膜，第一多晶硅层和第一氮化物膜的三个层，并用条纹状的列线进行图案化。分别在柱状线的侧壁上形成第二氮化物膜。在未被第一和第二氮化物膜覆盖的硅衬底表面上形成元件隔离绝缘膜。在去除第一和第二氮化物膜之后，在第一多晶硅层的侧壁上形成第一绝缘膜。随后，沉积包括第二绝缘膜和第二多晶硅层的至少两层，并且通过相应地处理第二多晶硅层来形成与柱状线垂直延伸的横线的图案。即使在形成元件隔离绝缘膜之后，也可以抑制其远端部分的栅极氧化膜的增厚，从而可以使基于热电子和隧道现象的电子注入特性的变化和劣化最小化。

3. 发明授权

US06211546B1 Method of manufacturing nonvolatile semiconductor memory device 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US06211546B1
公开(公告)日：2001-04-03
申请号：US09217811
申请日：1998-12-22
申请人： Masataka Kato , Tetsuo Adachi , Hitoshi Kume , Shoji Shukuri
发明人： Masataka Kato , Tetsuo Adachi , Hitoshi Kume , Shoji Shukuri
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , Y10S257/90
摘要： A method of manufacturing a nonvolatile semiconductor memory device which is protected against deterioration in the electron injection/discharge characteristics between a floating gate of a memory cell and a channel. Three layers including a gate oxide film, a first polysilicon layer and a first nitride film are sequentially deposited on a silicon substrate surface and patterned with stripe-like columnwise lines. A second nitride film is formed on side walls of the columnwise lines, respectively. An element isolating insulation film is formed on the silicon substrate surface which is not covered with the first and second nitride films. After removal of the first and second nitride films, a first insulation film is formed on the side walls of the first polysilicon layer. Subsequently, at least two layers including a second insulation film and a second polysilicon layer are deposited and a pattern of rowwise lines extending orthogonally to the columnwise lines are formed by processing correspondingly the second polysilicon layer. Even after formation of the element isolating insulation film, thickening of the gate oxide film at distal portions thereof can be suppressed, whereby variations and deterioration in the characteristic of electron injection based on hot electron and tunnel phenomena can be minimized.
摘要翻译：一种制造非易失性半导体存储器件的方法，其被保护以防止存储单元的浮置栅极和沟道之间的电子注入/放电特性的劣化。在硅衬底表面上依次沉积包括栅极氧化膜，第一多晶硅层和第一氮化物膜的三个层，并用条纹状的列线进行图案化。分别在柱状线的侧壁上形成第二氮化物膜。在未被第一和第二氮化物膜覆盖的硅衬底表面上形成元件隔离绝缘膜。在去除第一和第二氮化物膜之后，在第一多晶硅层的侧壁上形成第一绝缘膜。随后，沉积包括第二绝缘膜和第二多晶硅层的至少两层，并且通过相应地处理第二多晶硅层来形成与柱状线垂直延伸的横线的图案。即使在形成元件隔离绝缘膜之后，也可以抑制其远端部分的栅极氧化膜的增厚，从而可以使基于热电子和隧道现象的电子注入特性的变化和劣化最小化。

4. 发明授权

US5672529A Method of manufacturing nonvolatile semiconductor memory device 失效
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US5672529A
公开(公告)日：1997-09-30
申请号：US413263
申请日：1995-03-30
申请人： Masataka Kato , Tetsuo Adachi , Hitoshi Kume , Shoji Shukuri
发明人： Masataka Kato , Tetsuo Adachi , Hitoshi Kume , Shoji Shukuri
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265
CPC分类号： H01L27/11521 , Y10S257/90
摘要： A method of manufacturing a nonvolatile semiconductor memory device which is protected against deterioration in the electron injection/discharge characteristics between a floating gate of a memory cell and a channel. Three layers including a gate oxide film, a first polysilicon layer and a first nitride film are sequentially deposited on a silicon substrate surface and patterned with stripe-like columnwise lines. A second nitride film is formed on side walls of the columnwise lines, respectively. An element isolating insulation film is formed on the silicon substrate surface which is not covered with the first and second nitride films. After removal of the first and second nitride films, a first insulation film is formed on the side walls of the first polysilicon layer. Subsequently, at least two layers including a second insulation film and a second polysilicon layer are deposited and a pattern of rowwise lines extending orthogonally to the columnwise lines are formed by processing correspondingly the second polysilicon layer. Even after formation of the element isolating insulation film, thickening of the gate oxide film at distal portions thereof can be suppressed, whereby variations and deterioration in the characteristic of electron injection based on hot electron and tunnel phenomena can be minimized.
摘要翻译：一种制造非易失性半导体存储器件的方法，其被保护以防止存储单元的浮置栅极和沟道之间的电子注入/放电特性的劣化。在硅衬底表面上依次沉积包括栅极氧化膜，第一多晶硅层和第一氮化物膜的三个层，并用条纹状的列线进行图案化。分别在柱状线的侧壁上形成第二氮化物膜。在未被第一和第二氮化物膜覆盖的硅衬底表面上形成元件隔离绝缘膜。在去除第一和第二氮化物膜之后，在第一多晶硅层的侧壁上形成第一绝缘膜。随后，沉积包括第二绝缘膜和第二多晶硅层的至少两层，并且通过相应地处理第二多晶硅层来形成与柱状线垂直延伸的横线的图案。即使在形成元件隔离绝缘膜之后，也可以抑制其远端部分的栅极氧化膜的增厚，从而可以使基于热电子和隧道现象的电子注入特性的变化和劣化最小化。

5. 发明授权

US5814543A Method of manufacturing a semicondutor integrated circuit device having nonvolatile memory cells 失效
标题翻译：具有非易失性存储单元的半导体集成电路器件的制造方法
公开(公告)号：US5814543A
公开(公告)日：1998-09-29
申请号：US562021
申请日：1995-11-22
申请人： Toshiaki Nishimoto , Shoji Shukuri , Tsutomu Okazaki , Hideo Tobe , Kazuhiro Komori , Masataka Kato , Hitoshi Kume
发明人： Toshiaki Nishimoto , Shoji Shukuri , Tsutomu Okazaki , Hideo Tobe , Kazuhiro Komori , Masataka Kato , Hitoshi Kume
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating a semiconductor integrated circuit device comprising a nonvolatile memory cell, comprises the steps of forming a first gate material which comprises a silicon film containing no impurities, whose top surface is covered with an oxidation-resistant mask, and whose width in the gate-length direction is prescribed, on part of the surface of a first gate insulating film, forming a thermal-oxidation insulating film on the surface of an active region of a semiconductor substrate through thermal oxidation, removing an oxidation-resistant mask, forming a second gate material which comprises a silicon film into which impurities are introduced and whose width in the gate-length direction is prescribed, on each surface of the thermal-oxidation insulating film and the first gate material forming a second gate insulating film on the surface of the second gate material, and forming a third gate material on the surface of the second gate insulating film.
摘要翻译：一种制造包括非易失性存储单元的半导体集成电路器件的方法，包括以下步骤：形成第一栅极材料，该第一栅极材料包括不含杂质的硅膜，其顶表面被抗氧化掩模覆盖，并且其宽度在在第一栅极绝缘膜的一部分表面上规定栅极长度方向，通过热氧化在半导体衬底的有源区的表面上形成热氧化绝缘膜，去除抗氧化掩模，形成第二栅极材料，其包括在所述热氧化绝缘膜和形成第二栅极绝缘膜的表面上的所述热氧化绝缘膜和所述第一栅极材料的表面上引入了杂质并规定了栅极长度方向的宽度的硅膜第二栅极材料，并在第二栅极绝缘膜的表面上形成第三栅极材料。

6. 发明授权

US06617632B2 Semiconductor device and a method of manufacturing the same 有权
公开(公告)号：US06617632B2
公开(公告)日：2003-09-09
申请号：US10005300
申请日：2001-12-07
申请人： Yasuhiro Taniguchi , Kazuyoshi Shiba , Nozomu Matsuzaki , Hidenori Takada , Hitoshi Kume , Shoji Shukuri
发明人： Yasuhiro Taniguchi , Kazuyoshi Shiba , Nozomu Matsuzaki , Hidenori Takada , Hitoshi Kume , Shoji Shukuri
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11546
摘要： A parallel connection-type nonvolatile memory semiconductor device comprises a plurality of memory cells disposed on a semiconductor substrate in matrix form, each including a gate insulating film, a floating gate electrode, an interlayer film and a control gate electrode successively formed so as to cover a channel region on a main surface of the semiconductor substrate, of a first conductivity type; a second conductivity type source and drain regions formed on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing a second conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially lower than the drain region in impurity concentration; and a punch-through stopper layer which is adjacent to the first semiconductor region and formed by introducing a first conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially higher than the channel region in impurity concentration, and wherein the source regions and drain regions of the plurality of nonvolatile memory cells are parallel-connected to one another in respective columns, word lines some of which constitute the control gate electrodes of the plurality of nonvolatile memory cells, extend in respective rows, a voltage is applied to at least one word line, which is set so as to serve as a selected word line, and when carriers are stored in a floating gate electrode of each selected memory cell, a negative voltage is applied to other non-selected word lines other than the selected word line.

7. 发明授权

US08222686B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08222686B2
公开(公告)日：2012-07-17
申请号：US13097731
申请日：2011-04-29
申请人： Shoji Shukuri
发明人： Shoji Shukuri
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/34 , H01L21/28273 , H01L21/28282 , H01L23/535 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/1157 , H01L27/11573 , H01L29/42328 , H01L29/42344 , H01L29/42368 , H01L29/45 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a nonvolatile memory cell which includes a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and being adjacent to the control gate electrode, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, the control gate electrode having a different type conductivity than that of the memory gate electrode. A manufacturing technique for a semiconductor device including a nonvolatile memory cell having control gate and memory gate electrodes is also featured.
摘要翻译：一种具有非易失性存储单元的半导体器件，包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的控制电极，用作控制栅电极的栅极绝缘体的第一绝缘膜，形成在所述半导体衬底上的第二绝缘膜，以及形成在所述第二绝缘膜上并与所述控制栅电极相邻的存储栅电极，所述第二绝缘膜用作所述存储栅电极的栅极绝缘体，并且具有非导电电荷所述控制栅电极具有与所述存储栅电极不同的导电类型。还提出了一种包括具有控制栅极和存储栅电极的非易失性存储单元的半导体器件的制造技术。

8. 发明申请

US20120112265A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120112265A1
公开(公告)日：2012-05-10
申请号：US13350703
申请日：2012-01-13
申请人： Natsuo AJIKA , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo AJIKA , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L29/792
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

9. 发明申请

US20100149875A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100149875A1
公开(公告)日：2010-06-17
申请号：US12714750
申请日：2010-03-01
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C16/04 , G11C7/10 , G11C16/06
CPC分类号： G11C16/3436
摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
摘要翻译：非易失性半导体存储器技术领域本发明涉及非易失性半导体存储器，更具体地说涉及具有增加的程序吞吐量的非易失性半导体存储器本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

10. 发明申请

US20090090961A1 Non-Volatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090090961A1
公开(公告)日：2009-04-09
申请号：US12246193
申请日：2008-10-06
申请人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L29/792
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

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