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1. 发明授权

US5870618A Processor and data processor 失效
标题翻译：处理器和数据处理器
公开(公告)号：US5870618A
公开(公告)日：1999-02-09
申请号：US681180
申请日：1996-07-22
申请人： Yoshifumi Fujikawa , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Masao Ishiguro
发明人： Yoshifumi Fujikawa , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Masao Ishiguro
IPC分类号： G06F9/305 , G06F9/30 , G06F9/302 , G06F9/34 , G06F9/38 , G06F9/26
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30101
摘要： An object of the present invention is to provide a processor which can execute calculation between data of a data length larger than the data length of the register file at high speed without the cost of the hardware being increased so much and the first long register 12 and the second long register 13 having a bit width which is two times of the bit width of the register file and the long register update device 14 for updating the data of the second long register 13 partially are installed between the register file 2 and the pixel calculator 11. When the long register update pixel calculation instruction is stored in the instruction register 31, the long register update device 14 connects a part of the data of the second long register 13 and a part of data read from the register file 2 and sends them to the pixel calculator 11 and the second long register 13 via the selector 15. The pixel calculator 11 executes calculation between the data of the first long register 12 and the data given from the selector 15.
摘要翻译：本发明的目的是提供一种处理器，其可以在高速的数据长度大于寄存器文件的数据长度的数据长度的数据之间进行计算，而不会增加硬件的成本，并且第一长寄存器12和具有位宽度为寄存器堆的位宽度的二倍的第二长寄存器13和用于更新第二长寄存器13的数据的长寄存器更新装置14部分地安装在寄存器堆2和像素计算器当长寄存器更新像素计算指令存储在指令寄存器31中时，长寄存器更新装置14连接第二长寄存器13的数据的一部分和从寄存器文件2读取的数据的一部分，并将它们发送经由选择器15传送到像素计算器11和第二长寄存器13.像素计算器11执行第一长寄存器12的数据和数据gi之间的计算从选择器15发出。

2. 发明授权

US5893143A Parallel processing unit with cache memories storing NO-OP mask bits for instructions 失效
标题翻译：并行处理单元具有高速缓存存储器，用于存储用于指令的NO-OP掩码位
公开(公告)号：US5893143A
公开(公告)日：1999-04-06
申请号：US667670
申请日：1996-06-21
申请人： Kazuhiko Tanaka , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Yoshifumi Fujikawa , Masao Ishiguro
发明人： Kazuhiko Tanaka , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Yoshifumi Fujikawa , Masao Ishiguro
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/0875 , G06F9/3885
摘要： Each processing unit 110a to 110d has an individual cache memory 100a to 100d. When the cache memories read an instruction from a main storage 5, an instruction field is distributed to the cache memories. Each cache memory is controlled by a common control circuit 20. A compiler operates to schedule the processes so as to focus the processes to be executed on a specific processing unit. According to the scheduled processes, the volumes of the cache memories 100a to 100d are specified according to each execution ratio of the corresponding processing units to the cache memories. In the foregoing arrangement, a processor provides the processing units controlled by a sole program counter and improves processing by improving the efficiency of the cache memory. Further, the processor improves the efficiency of the cache memory by deleting unnecessary codes.
摘要翻译：每个处理单元110a至110d具有单独的高速缓冲存储器100a至100d。当高速缓冲存储器读取来自主存储器5的指令时，指令字段被分配到高速缓冲存储器。每个高速缓冲存储器由公共控制电路20控制。编译器操作以调度处理，以将要执行的处理集中在特定处理单元上。根据调度处理，根据相应的处理单元与高速缓冲存储器的各个执行率来指定高速缓冲存储器100a至100d的容量。在上述布置中，处理器提供由唯一程序计数器控制的处理单元，并且通过提高高速缓冲存储器的效率来改进处理。此外，处理器通过删除不必要的代码来提高高速缓冲存储器的效率。

3. 发明授权

US5872964A Comparison operating unit and graphic operating system 失效
标题翻译：比较操作单元和图形操作系统
公开(公告)号：US5872964A
公开(公告)日：1999-02-16
申请号：US693896
申请日：1996-08-05
申请人： Masao Ishiguro , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Yoshifumi Fujikawa
发明人： Masao Ishiguro , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Yoshifumi Fujikawa
IPC分类号： G06F7/02 , G06F9/30 , G06F9/305 , G06F9/38
CPC分类号： G06F9/30021 , G06F9/3885
摘要： A unit for efficiently carrying out a comparison operation and making it possible to prevent a generation of a disturbance in a pipeline during a pipeline operation is provided. This unit includes a first storage unit for storing storage information on two data to be compared, kind of comparison operation and result of comparison operation respectively, a second storage unit for storing said two data, kind of comparison operation and result of comparison operation, an operating unit for carrying out a predetermined plurality of kinds of comparison operations for two data, a selecting unit for selecting any one of results of comparison operation, and a processing unit for carrying out a processing of a comparison operation. The processing unit checks a storage destination of two data to be compared, gives the two data to the operating unit, checks a storage destination of a kind of a comparison operation, controls the selecting unit to select a result of an operation corresponding to the kind of comparison operation, and stores the operation result into a storage destination in the second storage unit.
摘要翻译：提供一种用于有效地执行比较操作并且可以防止在管道操作期间在管道中产生干扰的单元。该单元包括：第一存储单元，用于存储关于要比较的两个数据的存储信息，比较操作的种类和比较操作的结果;用于存储所述两个数据的第二存储单元，比较操作的种类和比较操作的结果; 操作单元，用于对两个数据执行预定的多种比较操作;选择单元，用于选择比较结果的任一个;以及处理单元，用于执行比较操作的处理。处理单元检查要比较的两个数据的存储目的地，将两个数据给予操作单元，检查比较操作的种类的存储目的地，控制选择单元选择与该种类对应的操作的结果并将运算结果存储在第二存储单元中的存储目的地。

4. 发明授权

US06608625B1 Three dimensional graphic processor 有权
标题翻译：三维图形处理器
公开(公告)号：US06608625B1
公开(公告)日：2003-08-19
申请号：US09173289
申请日：1998-10-14
申请人： Ken C. Chin , Masao Ishiguro , Keiji Kojima , Semyon Nisenzon
发明人： Ken C. Chin , Masao Ishiguro , Keiji Kojima , Semyon Nisenzon
IPC分类号： G06T100
CPC分类号： G06T15/50 , G06T15/005 , G06T15/80
摘要： A multimedia processor for performing three dimensional graphics processing in an integrated circuit comprises a microprocessor circuit which is configured to generate triangle set-up information corresponding to a plurality of triangles that define a three-dimensional object displayed on a screen. The screen is defined by a plurality of bins having a predetermined number of pixels. A data cache is coupled to the microprocessor and configured to store the set-up information. A three-dimensional triangle rasterizer is coupled to the data cache and configured to perform bin allocation to the triangles so as to identify all bins that intersect with a triangle on the screen.
摘要翻译：用于在集成电路中执行三维图形处理的多媒体处理器包括微处理器电路，其被配置为生成对应于定义屏幕上显示的三维对象的多个三角形的三角形建立信息。屏幕由具有预定数量像素的多个存储体定义。数据高速缓存耦合到微处理器并被配置为存储建立信息。三维三角形光栅化器耦合到数据高速缓存并且被配置为对三角形执行箱分配，以便识别与屏幕上的三角形相交的所有箱。

5. 发明申请

US20070126936A1 Digital broadcasting receiving apparatus and receiving method 审中-公开
标题翻译：数字广播接收装置和接收方法
公开(公告)号：US20070126936A1
公开(公告)日：2007-06-07
申请号：US11595906
申请日：2006-11-13
申请人： Toru Fujihira , Masao Ishiguro , Takashi Tashiro
发明人： Toru Fujihira , Masao Ishiguro , Takashi Tashiro
IPC分类号： H04N5/46
CPC分类号： H04N5/4401 , H04N19/61 , H04N21/44209 , H04N21/4621 , H04N21/631
摘要： According to the invention, in digital television broadcasting by a hierarchical transmission method, even if the receiving condition deteriorates and gives rise to any uncorrectable transmission error in streams, the deterioration of the quality of video and audio signals can be restrained to the minimum. The digital broadcasting receiving apparatus, after separating transmission streams of a plurality of levels into video and audio basic streams, subdivides the data of each stream and detects any error. Data which have been normally decoded are selected according to the relative priority of a designated level macro-block by macro-block or slice by slice for video data and frame by frame for audio data, and video and audio signals are thereby generated. Boundary parts of data of different levels are smoothed.
摘要翻译：根据本发明，在分层传输方法的数字电视广播中，即使接收条件恶化并且在流中引起任何不可校正的传输错误，也可以将视频和音频信号的质量的劣化抑制到最小。数字广播接收装置在将多个级别的传输流分离为视频和音频基本流之后，对每个流的数据进行细分并检测任何错误。根据指定的级别宏块的相对优先级，通过宏块或视频数据的逐个片段以及逐帧的音频数据来选择正常解码的数据，从而生成视频和音频信号。不同级别数据的边界部分平滑。

6. 发明申请

US20050223404A1 Digital broadcasting receiver, digital signal processor, and control method for digital broadcasting receiver 审中-公开
标题翻译：数字广播接收机，数字信号处理器和数字广播接收机的控制方法
公开(公告)号：US20050223404A1
公开(公告)日：2005-10-06
申请号：US11061797
申请日：2005-02-17
申请人： Masao Ishiguro , Yukio Fujii , Atsuo Kawaguchi
发明人： Masao Ishiguro , Yukio Fujii , Atsuo Kawaguchi
IPC分类号： H04N5/44 , H04N5/445 , H04N7/173 , H04N5/217
CPC分类号： H04N5/445 , H04N5/4401 , H04N21/42204 , H04N21/434 , H04N21/485 , H04N21/8543
摘要： An apparatus and a control method for an apparatus includes: a tuner for transmitting a demodulation signal which is a signal generated by demodulating a receiving signal of a digital broadcast; a digital signal processor for decoding the demodulation signal and transmitting a first video signal to an external device; a general-purpose processor for generating a second video signal to be synthesized with the first video signal; a video signal synthesizing circuit for synthesizing the second video signal with the first video signal; and a user interface for accepting from the external device an input of a starting signal which is a signal instructing a start of video signal output. The digital signal processor and the general-purpose processor start respective boot sequences in response to the acceptance of input of the starting signal by the user interface, and the digital signal processor starts the decoding of the demodulation signal before the boot sequence of the general-purpose processor is completed.
摘要翻译：一种用于装置的装置和控制方法，包括：调谐器，用于发送解调信号，该解调信号是通过解调数字广播的接收信号而产生的信号; 数字信号处理器，用于解码解调信号并将第一视频信号发送到外部设备; 用于产生要与第一视频信号合成的第二视频信号的通用处理器; 用于将第二视频信号与第一视频信号合成的视频信号合成电路; 以及用于从外部设备接收作为指示视频信号输出开始的信号的起始信号的输入的用户界面。数字信号处理器和通用处理器响应于用户接口接收到起始信号的输入而启动相应的引导序列，并且数字信号处理器在通用接口的引导顺序之前开始对解调信号的解码，目的处理器完成。

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