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1. 发明授权

US5870618A Processor and data processor 失效
标题翻译：处理器和数据处理器
公开(公告)号：US5870618A
公开(公告)日：1999-02-09
申请号：US681180
申请日：1996-07-22
申请人： Yoshifumi Fujikawa , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Masao Ishiguro
发明人： Yoshifumi Fujikawa , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Masao Ishiguro
IPC分类号： G06F9/305 , G06F9/30 , G06F9/302 , G06F9/34 , G06F9/38 , G06F9/26
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30101
摘要： An object of the present invention is to provide a processor which can execute calculation between data of a data length larger than the data length of the register file at high speed without the cost of the hardware being increased so much and the first long register 12 and the second long register 13 having a bit width which is two times of the bit width of the register file and the long register update device 14 for updating the data of the second long register 13 partially are installed between the register file 2 and the pixel calculator 11. When the long register update pixel calculation instruction is stored in the instruction register 31, the long register update device 14 connects a part of the data of the second long register 13 and a part of data read from the register file 2 and sends them to the pixel calculator 11 and the second long register 13 via the selector 15. The pixel calculator 11 executes calculation between the data of the first long register 12 and the data given from the selector 15.
摘要翻译：本发明的目的是提供一种处理器，其可以在高速的数据长度大于寄存器文件的数据长度的数据长度的数据之间进行计算，而不会增加硬件的成本，并且第一长寄存器12和具有位宽度为寄存器堆的位宽度的二倍的第二长寄存器13和用于更新第二长寄存器13的数据的长寄存器更新装置14部分地安装在寄存器堆2和像素计算器当长寄存器更新像素计算指令存储在指令寄存器31中时，长寄存器更新装置14连接第二长寄存器13的数据的一部分和从寄存器文件2读取的数据的一部分，并将它们发送经由选择器15传送到像素计算器11和第二长寄存器13.像素计算器11执行第一长寄存器12的数据和数据gi之间的计算从选择器15发出。

2. 发明授权

US5893143A Parallel processing unit with cache memories storing NO-OP mask bits for instructions 失效
标题翻译：并行处理单元具有高速缓存存储器，用于存储用于指令的NO-OP掩码位
公开(公告)号：US5893143A
公开(公告)日：1999-04-06
申请号：US667670
申请日：1996-06-21
申请人： Kazuhiko Tanaka , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Yoshifumi Fujikawa , Masao Ishiguro
发明人： Kazuhiko Tanaka , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Yoshifumi Fujikawa , Masao Ishiguro
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/0875 , G06F9/3885
摘要： Each processing unit 110a to 110d has an individual cache memory 100a to 100d. When the cache memories read an instruction from a main storage 5, an instruction field is distributed to the cache memories. Each cache memory is controlled by a common control circuit 20. A compiler operates to schedule the processes so as to focus the processes to be executed on a specific processing unit. According to the scheduled processes, the volumes of the cache memories 100a to 100d are specified according to each execution ratio of the corresponding processing units to the cache memories. In the foregoing arrangement, a processor provides the processing units controlled by a sole program counter and improves processing by improving the efficiency of the cache memory. Further, the processor improves the efficiency of the cache memory by deleting unnecessary codes.
摘要翻译：每个处理单元110a至110d具有单独的高速缓冲存储器100a至100d。当高速缓冲存储器读取来自主存储器5的指令时，指令字段被分配到高速缓冲存储器。每个高速缓冲存储器由公共控制电路20控制。编译器操作以调度处理，以将要执行的处理集中在特定处理单元上。根据调度处理，根据相应的处理单元与高速缓冲存储器的各个执行率来指定高速缓冲存储器100a至100d的容量。在上述布置中，处理器提供由唯一程序计数器控制的处理单元，并且通过提高高速缓冲存储器的效率来改进处理。此外，处理器通过删除不必要的代码来提高高速缓冲存储器的效率。

3. 发明授权

US5872964A Comparison operating unit and graphic operating system 失效
标题翻译：比较操作单元和图形操作系统
公开(公告)号：US5872964A
公开(公告)日：1999-02-16
申请号：US693896
申请日：1996-08-05
申请人： Masao Ishiguro , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Yoshifumi Fujikawa
发明人： Masao Ishiguro , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Yoshifumi Fujikawa
IPC分类号： G06F7/02 , G06F9/30 , G06F9/305 , G06F9/38
CPC分类号： G06F9/30021 , G06F9/3885
摘要： A unit for efficiently carrying out a comparison operation and making it possible to prevent a generation of a disturbance in a pipeline during a pipeline operation is provided. This unit includes a first storage unit for storing storage information on two data to be compared, kind of comparison operation and result of comparison operation respectively, a second storage unit for storing said two data, kind of comparison operation and result of comparison operation, an operating unit for carrying out a predetermined plurality of kinds of comparison operations for two data, a selecting unit for selecting any one of results of comparison operation, and a processing unit for carrying out a processing of a comparison operation. The processing unit checks a storage destination of two data to be compared, gives the two data to the operating unit, checks a storage destination of a kind of a comparison operation, controls the selecting unit to select a result of an operation corresponding to the kind of comparison operation, and stores the operation result into a storage destination in the second storage unit.
摘要翻译：提供一种用于有效地执行比较操作并且可以防止在管道操作期间在管道中产生干扰的单元。该单元包括：第一存储单元，用于存储关于要比较的两个数据的存储信息，比较操作的种类和比较操作的结果;用于存储所述两个数据的第二存储单元，比较操作的种类和比较操作的结果; 操作单元，用于对两个数据执行预定的多种比较操作;选择单元，用于选择比较结果的任一个;以及处理单元，用于执行比较操作的处理。处理单元检查要比较的两个数据的存储目的地，将两个数据给予操作单元，检查比较操作的种类的存储目的地，控制选择单元选择与该种类对应的操作的结果并将运算结果存储在第二存储单元中的存储目的地。

4. 发明授权

US6041399A VLIW system with predicated instruction execution for individual instruction fields 失效
标题翻译：具有针对各个指令字段执行预定指令的VLIW系统
公开(公告)号：US6041399A
公开(公告)日：2000-03-21
申请号：US884667
申请日：1997-06-27
申请人： Koichi Terada , Keiji Kojima , Yoshifumi Fujikawa , Tohru Nojiri , Kiyokazu Nishioka
发明人： Koichi Terada , Keiji Kojima , Yoshifumi Fujikawa , Tohru Nojiri , Kiyokazu Nishioka
IPC分类号： G06F9/30 , G06F9/32 , G06F9/34 , G06F9/38 , G06F9/45
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/3824
摘要： In the case of constituting a processing unit having the characteristic of a VLIW type processing unit and the characteristic of a pipeline type processing unit, since reference to the result of operations is made among a plurality of processing units executing in parallel the operations, transfer of the register file is frequently generated among the processing units, resulting in insufficient effect of the high speed operations. In view of solving this problem, the predicate registers are provided and moreover a means for broadcasting the update data of the predicate register to all processing units is also provided. Thereby, operations for obtaining branching condition and numerical value can be realized in different processing units and the number of steps of the processing program can be reduced. In addition, since high speed transfer between the processing units of the data register having a wider bit width is no longer required and thereby the mounting area can be reduced and high speed processing unit can be realized.
摘要翻译：在构成具有VLIW类型处理单元的特征的处理单元和流水线类型处理单元的特性的情况下，由于在并行执行操作的多个处理单元中进行操作结果的参考，因此，在处理单元之间经常生成寄存器文件，导致高速操作的效果不足。为了解决这个问题，提供了谓词寄存器，并且还提供了用于向所有处理单元广播谓词寄存器的更新数据的装置。因此，可以在不同的处理单元中实现获得分支条件和数值的操作，并且可以减少处理程序的步数。此外，由于不再需要具有较宽位宽的数据寄存器的处理单元之间的高速传输，从而可以减小安装面积，并可实现高速处理单元。

5. 发明授权

US06965981B2 Processor including a plurality of computing devices 失效
标题翻译：处理器包括多个计算设备
公开(公告)号：US06965981B2
公开(公告)日：2005-11-15
申请号：US10053683
申请日：2002-01-24
申请人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
发明人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
IPC分类号： G06F9/318 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3891 , G06F9/30036 , G06F9/30112 , G06F9/30167 , G06F9/30178 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/3802 , G06F9/3816 , G06F9/3822 , G06F9/3836 , G06F9/3853 , G06F9/3885 , G06F9/3887
摘要： As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
摘要翻译：就多媒体处理而言，通常同时执行同一类型的多个计算，因此使用具有相同功能的多个计算单元和用于通过一个计算单元的指令单元来控制多个单元的模式信息在每个指令中准备以执行具有单个指令的多个计算。

6. 发明申请

US20060053271A1 Processor 审中-公开
标题翻译：处理器
公开(公告)号：US20060053271A1
公开(公告)日：2006-03-09
申请号：US11216024
申请日：2005-09-01
申请人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
发明人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
IPC分类号： G06F9/30
CPC分类号： G06F9/3891 , G06F9/30036 , G06F9/30112 , G06F9/30167 , G06F9/30178 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/3802 , G06F9/3816 , G06F9/3822 , G06F9/3836 , G06F9/3853 , G06F9/3885 , G06F9/3887
摘要： An object of the present invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
摘要翻译：本发明的目的是提供一种能够以少量指令代码执行许多计算的处理器。就多媒体处理而言，通常同时执行同一类型的多个计算，因此使用具有相同功能的多个计算单元和用于通过一个计算单元的指令单元来控制多个单元的模式信息在每个指令中准备以执行具有单个指令的多个计算。

7. 发明授权

US06401190B1 Parallel computing units having special registers storing large bit widths 失效
标题翻译：具有专用寄存器的并行计算单元存储大的位宽
公开(公告)号：US06401190B1
公开(公告)日：2002-06-04
申请号：US08913840
申请日：1997-09-12
申请人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
发明人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
IPC分类号： G06F1500
CPC分类号： G06F9/3891 , G06F9/30036 , G06F9/30112 , G06F9/30167 , G06F9/30178 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/3802 , G06F9/3816 , G06F9/3822 , G06F9/3836 , G06F9/3853 , G06F9/3885 , G06F9/3887
摘要： An object of the prevent invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
摘要翻译：防止发明的一个目的是提供一种能够以少量指令代码执行许多计算的处理器。就多媒体处理而言，通常同时执行同一类型的多个计算，因此使用具有相同功能的多个计算单元和用于通过一个计算单元的指令单元来控制多个单元的模式信息在每个指令中准备以执行具有单个指令的多个计算。

8. 发明授权

US07337321B2 Digital content protection using invisible and visible watermarks 有权
标题翻译：数字内容保护使用隐形可见水印
公开(公告)号：US07337321B2
公开(公告)日：2008-02-26
申请号：US10230431
申请日：2002-08-29
申请人： Koichi Terada , Yukio Fujii , Yoshifumi Fujikawa , Taruhi Iwagaki
发明人： Koichi Terada , Yukio Fujii , Yoshifumi Fujikawa , Taruhi Iwagaki
IPC分类号： H04L9/00
CPC分类号： H04N1/32325 , G06T1/0021 , H04N1/32144 , H04N2201/3233 , H04N2201/3269 , H04N2201/327
摘要： A technique for distributing digital contents capable of effectively protecting copyrights and the like on the basis of invisible electronic watermark information and electronic watermark information is to be provided. On the sending side, additional information including copyright-related information is embedded into digital contents in advance as invisible electronic watermark information, while on the receiving side, additional information as the embedded invisible electronic watermark information is decoded and extracted as visible watermark information, the extracted information is embedded again into the digital contents, and the additional information is distributed or outputted as visible information together with the digital contents.
摘要翻译：提供一种用于分发基于不可见电子水印信息和电子水印信息有效保护版权等的数字内容的技术。在发送侧，包括版权相关信息的附加信息被预先嵌入到数字内容中作为不可见的电子水印信息，而在接收侧，作为嵌入的不可见电子水印信息的附加信息被解码并提取为可视水印信息，提取的信息再次嵌入到数字内容中，附加信息作为可视信息与数字内容一起分发或输出。

9. 发明申请

US20060236333A1 Music detection device, music detection method and recording and reproducing apparatus 审中-公开
标题翻译：音乐检测装置，音乐检测方法和记录和再现装置
公开(公告)号：US20060236333A1
公开(公告)日：2006-10-19
申请号：US11367557
申请日：2006-03-06
申请人： Yoshifumi Fujikawa , Kazushige Hiroi
发明人： Yoshifumi Fujikawa , Kazushige Hiroi
IPC分类号： H04N7/16 , H04H9/00
CPC分类号： H04H60/37
摘要： A method and device for detecting music parts within a content at relatively low cost of arithmetic operations. The device includes a first power calculating section for calculating a sum of powers of respective channels of two-channel sound, a second power calculating section for calculating a difference between the powers of the respective channels of the two-channel sound, a power ratio calculating section for calculating a ratio between the powers calculated by the first and second power calculating sections, a comparing section for comparing the ratio calculated by the power ratio calculating section with a prescribed threshold value, and a determination section for performing determination of a music segment based on a result of comparison by the comparing section.
摘要翻译：一种用于以相对低的算术成本检测内容内的音乐部分的方法和装置。该装置包括：第一功率计算部，用于计算双声道声音的各声道的功率之和;第二功率计算部，用于计算双声道声音的各声道的功率之间的差;功率比计算用于计算由第一和第二功率计算部分计算的功率之间的比率;比较部分，用于将由功率比计算部分计算的比率与规定的阈值进行比较;以及确定部分，用于执行基于音乐段的确定比较部分的比较结果。

10. 发明授权

US08218945B2 Motion picture recording/reproducing apparatus 有权
标题翻译：运动图像记录/再现装置
公开(公告)号：US08218945B2
公开(公告)日：2012-07-10
申请号：US11313829
申请日：2005-12-22
申请人： Kazushige Hiroi , Yoshifumi Fujikawa , Norikazu Sasaki , Riri Ueda , Akio Hayashi , Yukio Fujii , Atsuo Kawaguchi
发明人： Kazushige Hiroi , Yoshifumi Fujikawa , Norikazu Sasaki , Riri Ueda , Akio Hayashi , Yukio Fujii , Atsuo Kawaguchi
IPC分类号： H04N5/93 , G11B27/00 , G11B27/02 , G11B20/10 , G11B19/02 , G11B15/52 , G11B5/09
CPC分类号： H04N5/76 , H04N9/8205
摘要： A motion picture recording/reproducing apparatus for embodying the technique includes, at least, a motion picture data input unit which inputs the motion picture data, a storage unit which stores the motion picture data, a recording unit which stores the motion picture data in the storage unit, a feature generating unit which generates a feature of the motion picture data, a ranking generating unit which provides ranking of scenes in the motion picture data according to their importance levels, a reproduction scene deciding unit which decides a reproduction image for each of the scenes in the motion picture data, and a category acquiring unit which acquires the category of the motion picture data. The ranking generating unit provides ranking of the scenes in the input motion picture data on the basis of the acquired category.
摘要翻译：用于实施该技术的运动图像记录/再现装置至少包括输入运动图像数据的运动图像数据输入单元，存储运动图像数据的存储单元，存储运动图像数据的记录单元存储单元，产生运动图像数据的特征的特征生成单元，根据其重要性级别提供运动图像数据中的场景的排名的排名生成单元;再现场景决定单元，其为每个运动图像数据中的场景，以及获取运动图像数据的类别的类别获取单元。排序生成单元基于所获取的类别来提供输入运动图像数据中的场景的排名。

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