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    • 8. 发明授权
    • Error control apparatus and method using cyclic code
    • 使用循环码的错误控制装置和方法
    • US06516439B2
    • 2003-02-04
    • US09899062
    • 2001-07-06
    • Yukio KodamaTakeshi Kyomoto
    • Yukio KodamaTakeshi Kyomoto
    • H03M1300
    • H03M13/091H03M13/15H03M13/2703H03M13/29
    • An error control apparatus includes: a deinterleaver for deinterleaving data of a predetermined number of bits coded by predetermined cyclic codes, which is to be interleaved in accordance with a predetermined interleaving order; a first cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to a coding system of the cyclic code; and a second cyclic code checking circuit for receiving an output of the deinterleaver and making a cyclic code check on the data of the predetermined number of bits by a check system corresponding to the coding system of the cyclic code simultaneously with the cyclic code check by the first cyclic code checking circuit in substantially the same time while canceling an interleave effect by the deinterleaver.
    • 误差控制装置包括:去交织器,用于根据预定的交织顺序对由预定循环码编码的预定数量的比特进行交织的数据进行解交织; 第一循环码检查电路,用于接收解交织器的输出,并通过与循环码的编码系统相对应的检查系统对预定位数的数据进行循环码校验; 以及第二循环码检查电路,用于通过与所述循环码的编码系统相对应的检查系统对所述解交织器的输出进行接收,并对所述预定比特数的数据进行循环码校验, 第一循环码检测电路在消除交织器的交织效应的同时基本相同。
    • 9. 发明授权
    • Error correction circuit
    • 纠错电路
    • US5361266A
    • 1994-11-01
    • US138037
    • 1993-10-19
    • Yukio KodamaKazuo MurakamiHideo Yoshida
    • Yukio KodamaKazuo MurakamiHideo Yoshida
    • G11B20/18H03M13/00H03M13/29G06F11/10
    • H03M13/091H03M13/1515H03M13/159H03M13/29H03M13/6575
    • An error correction circuit is capable of performing correction errors in data at a high speed. A syndrome generator (2) calculates syndromes of RS codes based on partial data streams which are given from a data buffer (1). A received CRC generator (13) performs CRC coding on the partial data streams which are given from a data buffer (1) to thereby obtain received CRCs. An error pattern CRC generator (14) calculates error pattern CRCs of the respective partial data stream based on error patterns which are generated by an error pattern generation circuit (33). Under the control of a control circuit (40), the operations performed by the syndrome generator (2), the received CRC generator (13) and the error pattern CRC generator (14) are carried out at the same time. An improvement in the speed of error correction of the partial data streams performed by the error correction means directly leads to an improvement in the speed of the whole error correction.
    • 误差校正电路能够以高速执行数据中的校正误差。 校正子发生器(2)基于从数据缓冲器(1)给出的部分数据流来计算RS码的校验子。 接收到的CRC发生器(13)对从数据缓冲器(1)给出的部分数据流执行CRC编码,从而获得接收到的CRC。 错误模式CRC发生器(14)基于由错误模式产生电路(33)生成的错误模式来计算各部分数据流的错误模式CRC。 在控制电路(40)的控制下,由校正子发生器(2),接收到的CRC发生器(13)和错误模式CRC发生器(14)执行的操作同时进行。 由纠错装置执行的部分数据流的纠错速度的改善直接导致整个纠错的速度的提高。