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    • 1. 发明专利
    • Grinding plate manufacturing method
    • 研磨板制造方法
    • JP2010131236A
    • 2010-06-17
    • JP2008310773
    • 2008-12-05
    • Yukio KodamaLeben Hanbai:Kk幸男 児玉株式会社レーベン販売
    • KODAMA YUKIO
    • A47J43/25B21D28/00B21D28/10B21D53/00
    • PROBLEM TO BE SOLVED: To solve the problem that a punch and a die are complicated and the front end of the punch is formed to have a plane so as to consume a large amount of energy to perform punching concerning a conventional manufacturing method.
      SOLUTION: A grinding plate manufacturing tool includes: a press die 1; multiple polygonal pyramid projection teeth 1a arranged in the press die 1; a receiving die 2 to be fitted to the press die 1; and multiple columnar work pins 2a projecting in the receiving die 2, where the projection teeth 1a and the multiple work pins 2a are positioned not to mutually abutting when the press die 1 is fitted to the receiving die 2. By using the tool, an object 3 to be worked is positioned between the press die 1 and the receiving die 2 and the object 3 to be worked is held between the press die 1 and the receiving die 2, so as to break through the object 3 to be worked by the front ends of the multiple projection teeth 1a. Then, multiple swelling parts 4 are formed, where grinding edges are obtained in a plurality of front end projections 4a.
      COPYRIGHT: (C)2010,JPO&INPIT
    • 要解决的问题为了解决冲头和模具复杂的问题,并且冲头的前端形成为具有平面以便消耗大量的能量来进行关于常规制造方法的冲压 。 研磨板制造工具包括:压模1; 布置在压模1中的多个多角锥突起齿1a; 一个接纳模具2,装在压模1上; 以及在接收模具2中突出的多个柱状工作销2a,其中当压模1装配到接收模具2时,突出齿1a和多个工作销2a定位成不相互邻接。通过使用该工具, 3被定位在压模1和接收模具2之间,待加工的物体3保持在压模1和接收模具2之间,以便穿过被加工物体3被前端 多个突出齿1a的端部。 然后,形成多个膨胀部4,其中在多个前端突起4a中获得研磨边缘。 版权所有(C)2010,JPO&INPIT
    • 5. 发明授权
    • CRC code generation circuit, code error detection circuit and CRC
circuit having both functions of the CRC code generation circuit and
the code error detection circuit
    • CRC代码生成电路,代码错误检测电路和具有CRC码生成电路和代码错误检测电路的功能的CRC电路
    • US5935269A
    • 1999-08-10
    • US827061
    • 1997-03-26
    • Yukio KodamaKazuo Murakami
    • Yukio KodamaKazuo Murakami
    • H03M13/00
    • H03M13/09
    • When encoding data received by a dividing circuit and to be included in a CRC code word, the data is divided by a generator polynomial and remainder data resulting from the division is output from a plurality of parallel data output terminals of the dividing circuit. The remainder data is added to a CRC intrinsic value and "0" information in the adder to produce a sum. The sum is a CRC code for a CRC code word to be transmitted. When detecting code errors, data from a CRC code word is received by the dividing circuit, where the data is divided by the generator polynomial, and remainder data resulting from the division is output from the respective parallel data output terminals. The remainder data is added to the CRC intrinsic value and CRC code in the adder to produce a sum, and the sum is processed by a logical sum circuit to produce a logical sum output as a CRC flag. The CRC code generation and code error detection circuit generates CRC codes to be included in CRC code words at high speed and detects errors in received CRC code words at high speed.
    • 当对由分割电路接收并被包括在CRC码字中的数据进行编码时,由生成多项式除以数据,并且从划分电路的多个并行数据输出端输出从分频得到的余数。 剩余数据被加到CRC固有值和加法器中的“0”信息以产生和。 总和是要发送的CRC码字的CRC码。 当检测到码错误时,分频电路接收来自CRC码字的数据,其中数据被生成多项式除,并且从各个并行数据输出端子输出由除法产生的余数。 剩余数据被加到加法器中的CRC本征值和CRC码以产生和,并且由逻辑和电路处理和以产生逻辑和输出作为CRC标志。 CRC代码生成和代码错误检测电路以高速生成CRC代码字中包含的CRC代码,并以高速检测接收的CRC码字中的错误。
    • 6. 发明授权
    • CRC code generation circuit, code error detection circuit, and CRC
circuit having functions of both the CRC code generation circuit and
the code error detection circuit
    • CRC代码生成电路,代码错误检测电路以及具有CRC代码生成电路和代码错误检测电路两者的功能的CRC电路
    • US5898712A
    • 1999-04-27
    • US822209
    • 1997-03-21
    • Yukio KodamaKazuo Murakami
    • Yukio KodamaKazuo Murakami
    • G06F11/10H03M13/00H03M13/09H03M13/15
    • H03M13/15G06F11/10H03M13/09
    • When encoding data bits in a CRC code word and "0" information is received for every bit by a dividing circuit, the CRC code word is divided by a generation polynomial and remainder data resulting from the division is output from parallel data output terminals of the dividing circuit. The remainder data is added to a CRC intrinsic value in the adder to produce a sum. The sum is a CRC code in a CRC code word for transmission. When a code error is detected, data having a plurality of bits in a CRC code word and a CRC code are received by the dividing circuit, where they are divided by the generation polynomial and remainder data is output from the respective parallel data terminals. The remainder data is added to the CRC intrinsic value in the adder to produce a sum, and the sum is processed into a logical sum in a logical sum circuit. The logical sum is output as a CRC flag. The present invention provides a CRC code generation circuit for generating a CRC code in a CRC code word at high speed as well as a code error detection circuit for detecting a code error in a CRC code word at high speed.
    • 当编码CRC码字中的数据比特并且通过分频电路为每个比特接收到“0”信息时,将CRC码字除以生成多项式,并且从该除法得到的余数数据从并行数据输出端输出 分频电路。 剩余数据加到加法器中的CRC本征值以产生和。 该和是用于传输的CRC码字中的CRC码。 当检测到码错误时,分频电路接收CRC码字和CRC码中的多个位的数据,并将其除以生成多项式,并从各个并行数据终端输出余数。 剩余数据被加到加法器中的CRC本征值以产生和,并且该和被处理成逻辑和电路中的逻辑和。 逻辑和作为CRC标志输出。 本发明提供了一种用于以高速CRC码字生成CRC码的CRC码生成电路,以及用于以高速检测CRC码字中的码错误的码错误检测电路。
    • 7. 发明授权
    • Peak hold circuit
    • 峰值保持电路
    • US5134313A
    • 1992-07-28
    • US536472
    • 1990-06-12
    • Takehiko UmeyamaHideki MiyakeYukio Kodama
    • Takehiko UmeyamaHideki MiyakeYukio Kodama
    • G01R19/04G11C27/02
    • G01R19/04G11C27/02G11C27/024
    • In a sampling mode, a servo signal sampling and holding switch (4.sub.a) and a reference voltage sampling and holding switch (30.sub.a) are turned off, so that transistors (Q.sub.7a, Q.sub.5a) are turned on. In response to on states of the transistors (Q.sub.7a, Q.sub.5a), capacities (C.sub.3a, C.sub.30a) are charged with the peak voltage (V.sub.ref +(1/2)V.sub.s) of a servo signal and a reference voltage (V.sub.ref), respectively. In a holding mode, the sampling and holding switches (4.sub.a, 30.sub.a) are turned on, so that the transistors (Q.sub.7a, Q.sub.5a) are turned off. the charging voltages (D, E) of the capacitors (C.sub.3a, C.sub.30a) are discharged through post-stage buffers (5.sub.a, 3.sub.a), so that they include offsets which are canceled through a subtractor (6.sub.a).
    • 在采样模式中,伺服信号采样保持开关(4a)和参考电压采样保持开关(30a)截止,使晶体管(Q7a,Q5a)导通。 响应于晶体管(Q7a,Q5a)的导通状态,电容(C3a,C30a)分别以伺服信号的峰值电压(Vref +(1/2)Vs)和参考电压(Vref)充电。 在保持模式中,采样保持开关(4a,30a)导通,使得晶体管(Q7a,Q5a)截止。 电容器(C3a,C30a)的充电电压(D,E)通过后级缓冲器(5a,3a)放电,使得它们包括通过减法器(6a)消除的偏移。