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    • 1. 发明授权
    • Error correction circuit
    • 纠错电路
    • US5361266A
    • 1994-11-01
    • US138037
    • 1993-10-19
    • Yukio KodamaKazuo MurakamiHideo Yoshida
    • Yukio KodamaKazuo MurakamiHideo Yoshida
    • G11B20/18H03M13/00H03M13/29G06F11/10
    • H03M13/091H03M13/1515H03M13/159H03M13/29H03M13/6575
    • An error correction circuit is capable of performing correction errors in data at a high speed. A syndrome generator (2) calculates syndromes of RS codes based on partial data streams which are given from a data buffer (1). A received CRC generator (13) performs CRC coding on the partial data streams which are given from a data buffer (1) to thereby obtain received CRCs. An error pattern CRC generator (14) calculates error pattern CRCs of the respective partial data stream based on error patterns which are generated by an error pattern generation circuit (33). Under the control of a control circuit (40), the operations performed by the syndrome generator (2), the received CRC generator (13) and the error pattern CRC generator (14) are carried out at the same time. An improvement in the speed of error correction of the partial data streams performed by the error correction means directly leads to an improvement in the speed of the whole error correction.
    • 误差校正电路能够以高速执行数据中的校正误差。 校正子发生器(2)基于从数据缓冲器(1)给出的部分数据流来计算RS码的校验子。 接收到的CRC发生器(13)对从数据缓冲器(1)给出的部分数据流执行CRC编码,从而获得接收到的CRC。 错误模式CRC发生器(14)基于由错误模式产生电路(33)生成的错误模式来计算各部分数据流的错误模式CRC。 在控制电路(40)的控制下,由校正子发生器(2),接收到的CRC发生器(13)和错误模式CRC发生器(14)执行的操作同时进行。 由纠错装置执行的部分数据流的纠错速度的改善直接导致整个纠错的速度的提高。
    • 2. 发明授权
    • Code error detecting circuit
    • 代码错误检测电路
    • US5917841A
    • 1999-06-29
    • US748509
    • 1996-11-08
    • Yukio KodamaKazuo Murakami
    • Yukio KodamaKazuo Murakami
    • G06F11/10G11B20/18H03M13/00H03M13/09H03M13/15H04L1/00G06F11/00
    • H03M13/09H03M13/15
    • A Cyclic Redundancy Check (CRC) code word except a fixed pattern is provided to a code data input terminal of a division circuit in synchronization with a clock signal and divided at the division circuit, then, a remainder data of the division result is outputted from output terminals. The remainder data outputted from the output terminals is compared with a CRC inherent value at a comparison circuit, and a comparison result signal indicating whether the CRC code word includes errors is outputted. A temporary memory means takes in the comparison result signal in response to rise of a clock signal inputted into a clock signal input terminal, temporarily stores it, then output its storage contents as an error detecting signal via an output node.
    • 除了固定模式之外的循环冗余校验(CRC)码字被提供给与时钟信号同步的分频电路的码数据输入端,并在分频电路中分频,然后从分频电路输出除法结果的余数数据 输出端子。 将从输出端子输出的余数与比较电路的CRC固有值进行比较,并输出指示CRC码字是否包含错误的比较结果信号。 临时存储器装置响应于输入到时钟信号输入端的时钟信号的上升而接收比较结果信号,暂时存储,然后通过输出节点输出其存储内容作为错误检测信号。
    • 3. 发明授权
    • CRC code generation circuit for generating a CRC code and a code error
detection circuit for detecting a code error in a CRC code word
    • 用于产生CRC码的CRC码产生电路和用于检测CRC码字中的码错误的码错误检测电路
    • US5870413A
    • 1999-02-09
    • US820385
    • 1997-03-12
    • Yukio KodamaKazuo Murakami
    • Yukio KodamaKazuo Murakami
    • H03M13/00G06F11/10
    • H03M13/09
    • When encoding, data bits in a CRC code word are received for every bit by a dividing circuit where the CRC code word is divided by a generation polynomial and a remainder is output from parallel data output terminals. The remainder is added to a CRC intrinsic value and "0" information in the adder. The addition result is a CRC code in a CRC code word for transmission. When a code error is detected, data bits in a CRC code word and a CRC code are received for every bit by the dividing circuit, where they are divided by the generation polynomial and a remainder is output from the respective parallel data terminals. The remainder data is added to the CRC intrinsic value in the adder, and the result is further processed by a logical sum circuit. The logical sum is output as a CRC flag. The present invention provides a CRC code generation circuit for generating a CRC code in a CRC code word at high speed as well as a code error detection circuit for detecting a code error in a CRC code word at high speed.
    • 当编码时,通过分割电路为每个比特接收CRC码字中的数据比特,其中CRC码字被生成多项式除以余数由并行数据输出端输出。 其余部分加到CRC固有值,加法器中加上“0”信息。 相加结果是用于传输的CRC码字中的CRC码。 当检测到代码错误时,由分割电路为每个位接收CRC码字和CRC码中的数据位,并将其除以生成多项式,并从各个并行数据终端输出余数。 剩余数据被加到加法器中的CRC固有值,结果被逻辑和电路进一步处理。 逻辑和作为CRC标志输出。 本发明提供了一种用于以高速CRC码字生成CRC码的CRC码生成电路,以及用于以高速检测CRC码字中的码错误的码错误检测电路。
    • 4. 发明授权
    • CRC code generation circuit, code error detection circuit and CRC
circuit having both functions of the CRC code generation circuit and
the code error detection circuit
    • CRC代码生成电路,代码错误检测电路和具有CRC码生成电路和代码错误检测电路的功能的CRC电路
    • US5935269A
    • 1999-08-10
    • US827061
    • 1997-03-26
    • Yukio KodamaKazuo Murakami
    • Yukio KodamaKazuo Murakami
    • H03M13/00
    • H03M13/09
    • When encoding data received by a dividing circuit and to be included in a CRC code word, the data is divided by a generator polynomial and remainder data resulting from the division is output from a plurality of parallel data output terminals of the dividing circuit. The remainder data is added to a CRC intrinsic value and "0" information in the adder to produce a sum. The sum is a CRC code for a CRC code word to be transmitted. When detecting code errors, data from a CRC code word is received by the dividing circuit, where the data is divided by the generator polynomial, and remainder data resulting from the division is output from the respective parallel data output terminals. The remainder data is added to the CRC intrinsic value and CRC code in the adder to produce a sum, and the sum is processed by a logical sum circuit to produce a logical sum output as a CRC flag. The CRC code generation and code error detection circuit generates CRC codes to be included in CRC code words at high speed and detects errors in received CRC code words at high speed.
    • 当对由分割电路接收并被包括在CRC码字中的数据进行编码时,由生成多项式除以数据,并且从划分电路的多个并行数据输出端输出从分频得到的余数。 剩余数据被加到CRC固有值和加法器中的“0”信息以产生和。 总和是要发送的CRC码字的CRC码。 当检测到码错误时,分频电路接收来自CRC码字的数据,其中数据被生成多项式除,并且从各个并行数据输出端子输出由除法产生的余数。 剩余数据被加到加法器中的CRC本征值和CRC码以产生和,并且由逻辑和电路处理和以产生逻辑和输出作为CRC标志。 CRC代码生成和代码错误检测电路以高速生成CRC代码字中包含的CRC代码,并以高速检测接收的CRC码字中的错误。
    • 5. 发明授权
    • CRC code generation circuit, code error detection circuit, and CRC
circuit having functions of both the CRC code generation circuit and
the code error detection circuit
    • CRC代码生成电路,代码错误检测电路以及具有CRC代码生成电路和代码错误检测电路两者的功能的CRC电路
    • US5898712A
    • 1999-04-27
    • US822209
    • 1997-03-21
    • Yukio KodamaKazuo Murakami
    • Yukio KodamaKazuo Murakami
    • G06F11/10H03M13/00H03M13/09H03M13/15
    • H03M13/15G06F11/10H03M13/09
    • When encoding data bits in a CRC code word and "0" information is received for every bit by a dividing circuit, the CRC code word is divided by a generation polynomial and remainder data resulting from the division is output from parallel data output terminals of the dividing circuit. The remainder data is added to a CRC intrinsic value in the adder to produce a sum. The sum is a CRC code in a CRC code word for transmission. When a code error is detected, data having a plurality of bits in a CRC code word and a CRC code are received by the dividing circuit, where they are divided by the generation polynomial and remainder data is output from the respective parallel data terminals. The remainder data is added to the CRC intrinsic value in the adder to produce a sum, and the sum is processed into a logical sum in a logical sum circuit. The logical sum is output as a CRC flag. The present invention provides a CRC code generation circuit for generating a CRC code in a CRC code word at high speed as well as a code error detection circuit for detecting a code error in a CRC code word at high speed.
    • 当编码CRC码字中的数据比特并且通过分频电路为每个比特接收到“0”信息时,将CRC码字除以生成多项式,并且从该除法得到的余数数据从并行数据输出端输出 分频电路。 剩余数据加到加法器中的CRC本征值以产生和。 该和是用于传输的CRC码字中的CRC码。 当检测到码错误时,分频电路接收CRC码字和CRC码中的多个位的数据,并将其除以生成多项式,并从各个并行数据终端输出余数。 剩余数据被加到加法器中的CRC本征值以产生和,并且该和被处理成逻辑和电路中的逻辑和。 逻辑和作为CRC标志输出。 本发明提供了一种用于以高速CRC码字生成CRC码的CRC码生成电路,以及用于以高速检测CRC码字中的码错误的码错误检测电路。
    • 8. 发明授权
    • Motor-driven compressor
    • 电动压缩机
    • US08757989B2
    • 2014-06-24
    • US12547759
    • 2009-08-26
    • Kazuo Murakami
    • Kazuo Murakami
    • F04B35/04
    • F04C23/008F04C18/0215F04C29/0085F04C2240/803F04C2240/808H02K5/225H02K11/33
    • A motor-driven compressor includes a compression mechanism for compressing refrigerant, an electric motor for driving the compression mechanism, an inverter for controlling the operation of the electric motor, and a motor harness for electrically connecting the electric motor to the inverter. The compression mechanism and the electric motor are mechanically connected each other. The electric motor has first and second coil ends. The first coil end is located on the side of the compression mechanism and the inverter is located on the side of the second coil end. The motor harness is led out from the first coil end.
    • 电动压缩机包括用于压缩制冷剂的压缩机构,用于驱动压缩机构的电动机,用于控制电动机的操作的逆变器和用于将电动机电连接到逆变器的电动机线束。 压缩机构和电动机彼此机械连接。 电动机具有第一和第二线圈端部。 第一线圈端位于压缩机构的一侧,并且逆变器位于第二线圈端的一侧。 电动机线束从第一个线圈端引出。
    • 9. 发明授权
    • Motor-driven compressor
    • 电动压缩机
    • US08162626B2
    • 2012-04-24
    • US12333982
    • 2008-12-12
    • Hiroshi FukasakuTatsushi MoriKazuo MurakamiMasao IguchiMasahiro KawaguchiKen Suitou
    • Hiroshi FukasakuTatsushi MoriKazuo MurakamiMasao IguchiMasahiro KawaguchiKen Suitou
    • F04B17/00F04B35/04
    • H02K5/10F04C18/0215F04C23/008F04C27/00H02K5/12H02K7/14H02K11/33
    • A motor-driven compressor has a compression mechanism, a rotary shaft, an electric motor, a motor drive circuit, a connecting terminal and a housing assembly. The compression mechanism, the electric motor, and the motor drive circuit are disposed along the axial direction of the rotary shaft in the housing assembly having first through third housings. The first housing is used for mounting the electric motor and the compression mechanism. The second housing has a terminal mounting portion for fixing the connecting terminal. The first and second housings have fastening portions at the radially peripheral portion thereof. The third housing is joined to the second housing to form an accommodation space for accommodating the motor drive circuit. The closed casing is formed by fastening the fastening portions of the first and second housings by means of a first bolt and connecting the second housing to the open end of the first housing.
    • 电动压缩机具有压缩机构,旋转轴,电动马达,马达驱动电路,连接端子和壳体组件。 压缩机构,电动马达和马达驱动电路沿着具有第一至第三壳体的壳体组件中的旋转轴的轴向设置。 第一壳体用于安装电动机和压缩机构。 第二壳体具有用于固定连接端子的端子安装部。 第一和第二壳体在其径向周向部分处具有紧固部分。 第三壳体连接到第二壳体以形成用于容纳马达驱动电路的容置空间。 封闭的壳体通过借助于第一螺栓紧固第一和第二壳体的紧固部分并将第二壳体连接到第一壳体的开口端而形成。