会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Frequency modulation-type transmitting apparatus
    • 频率调制型发送装置
    • US08009835B2
    • 2011-08-30
    • US11528874
    • 2006-09-28
    • Masaki KinoshitaNobuo TakahashiSatoshi Terada
    • Masaki KinoshitaNobuo TakahashiSatoshi Terada
    • H04H20/47H04H20/88H04H40/36H04H20/48H04H40/45H03G3/00
    • H03G3/3036
    • A front-end processing circuit applies predetermined processing to an input signal and outputs a processed signal. A frequency modulation circuit applies frequency modulation to the output signal of the front-end processing circuit and outputs a processed signal. The front-end processing circuit includes a variable amplifier and a level detector. The variable amplifier receives a feedback signal and amplifies a signal by an amplification factor corresponding to the feedback signal. The level detector outputs the feedback signal to the variable amplifier in accordance with a level of a signal obtainable in a circuit succeeding the variable amplifier. The front-end processing circuit maintains the signal supplied to the frequency modulation circuit at a constant level.
    • 前端处理电路对输入信号进行预定处理并输出处理后的信号。 频率调制电路对前端处理电路的输出信号进行频率调制,并输出处理后的信号。 前端处理电路包括可变放大器和电平检测器。 可变放大器接收反馈信号并且通过与反馈信号对应的放大系数来放大信号。 电平检测器根据在可变放大器之后的电路中可获得的信号的电平将反馈信号输出到可变放大器。 前端处理电路将提供给频率调制电路的信号保持在恒定水平。
    • 2. 发明申请
    • Frequency modulation-type transmitting apparatus
    • 频率调制型发送装置
    • US20070076815A1
    • 2007-04-05
    • US11528874
    • 2006-09-28
    • Masaki KinoshitaNobuo TakahashiSatoshi Terada
    • Masaki KinoshitaNobuo TakahashiSatoshi Terada
    • H04L25/49
    • H03G3/3036
    • A front-end processing circuit applies predetermined processing to an input signal and outputs a processed signal. A frequency modulation circuit applies frequency modulation to the output signal of the front-end processing circuit and outputs a processed signal. The front-end processing circuit includes a variable amplifier and a level detector. The variable amplifier receives a feedback signal and amplifies a signal by an amplification factor corresponding to the feedback signal. The level detector outputs the feedback signal to the variable amplifier in accordance with a level of a signal obtainable in a circuit succeeding the variable amplifier. The front-end processing circuit maintains the signal supplied to the frequency modulation circuit at a constant level.
    • 前端处理电路对输入信号进行预定处理并输出处理后的信号。 频率调制电路对前端处理电路的输出信号进行频率调制,并输出处理后的信号。 前端处理电路包括可变放大器和电平检测器。 可变放大器接收反馈信号并且通过与反馈信号对应的放大系数来放大信号。 电平检测器根据在可变放大器之后的电路中可获得的信号的电平将反馈信号输出到可变放大器。 前端处理电路将提供给频率调制电路的信号保持在恒定水平。
    • 7. 发明申请
    • Frequency Divider Circuit
    • 分频电路
    • US20100201409A1
    • 2010-08-12
    • US12370326
    • 2009-02-12
    • Satoshi TeradaMasahiro ObuchiTadahiro Makabe
    • Satoshi TeradaMasahiro ObuchiTadahiro Makabe
    • H03B19/00H03K21/00
    • H03K23/40H03K21/12H03K23/50H03K23/667H03K23/68
    • A frequency divider circuit includes: a shift register capable of storing at least n-bit data configured to shift an input signal sequentially in synchronization with a clock signal; a pulse generating circuit configured to change the input signal into a pulse form in response to a change in logic level of an output signal from a stage of the shift register among n-bit output signals from the shift register, the stage corresponding to a bit resulting from shifting of the input signal by n bits; and a frequency dividing signal generating circuit configured to generate a frequency dividing signal whose logic level is inverted in response to a change in logic level of an output signal from any one stage of the shift register or logic level of the input signal, in order to divide the clock signal in frequency by a dividing ratio corresponding to the n bits.
    • 分频器电路包括:移位寄存器,其能够存储被配置为与时钟信号同步地顺序移位输入信号的至少n位数据; 脉冲发生电路,被配置为响应于来自移位寄存器的n位输出信号中的来自移位寄存器的级的输出信号的逻辑电平的变化而将输入信号改变为脉冲形式,对应于位 由输入信号移位n位导致的; 以及分频信号生成电路,其被配置为生成分频信号,该分频信号的逻辑电平响应于来自移位寄存器的任何一个级的输出信号或输入信号的逻辑电平的逻辑电平的变化而被反转,以便 将时钟信号的频率除以与n位对应的分频比。