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    • 1. 发明授权
    • Digital data processing circuit
    • 数字数据处理电路
    • US08090318B2
    • 2012-01-03
    • US12391933
    • 2009-02-24
    • Satoshi TeradaMasahiro ObuchiTadahiro Makabe
    • Satoshi TeradaMasahiro ObuchiTadahiro Makabe
    • H04B7/00
    • H04H20/61H04H60/80H04H2201/13
    • A digital data processing circuit includes: an output unit configured to output to an audio signal processing circuit change data for changing a receiving frequency of a FM receiving device as a first frequency to a second frequency in response to an instruction signal providing an instruction to change the receiving frequency to the second frequency, the audio signal processing circuit being a circuit configured to modulate a carrier wave having the first frequency corresponding to setting data with a modulation signal corresponding to an audio signal to be reproduced by the FM receiving device and to the change data, and transmit the modulated carrier wave to the FM receiving device; and a setting unit configured to set the setting data so as to change a frequency of the carrier wave to the second frequency after the output unit outputs the change data to the audio signal processing circuit.
    • 数字数据处理电路包括:输出单元,被配置为响应于提供改变指令的指令信号而输出到音频信号处理电路,用于将FM接收设备的接收频率作为第一频率改变为第二频率 对于第二频率的接收频率,音频信号处理电路是被配置为利用与要由FM接收装置再现的音频信号对应的调制信号来调制具有对应于设定数据的第一频率的载波的电路, 改变数据,并将调制载波传送到FM接收设备; 以及设定单元,被配置为在输出单元将改变数据输出到音频信号处理电路之后,将设置数据设置为将载波的频率改变为第二频率。
    • 5. 发明申请
    • Frequency Divider Circuit
    • 分频电路
    • US20100201409A1
    • 2010-08-12
    • US12370326
    • 2009-02-12
    • Satoshi TeradaMasahiro ObuchiTadahiro Makabe
    • Satoshi TeradaMasahiro ObuchiTadahiro Makabe
    • H03B19/00H03K21/00
    • H03K23/40H03K21/12H03K23/50H03K23/667H03K23/68
    • A frequency divider circuit includes: a shift register capable of storing at least n-bit data configured to shift an input signal sequentially in synchronization with a clock signal; a pulse generating circuit configured to change the input signal into a pulse form in response to a change in logic level of an output signal from a stage of the shift register among n-bit output signals from the shift register, the stage corresponding to a bit resulting from shifting of the input signal by n bits; and a frequency dividing signal generating circuit configured to generate a frequency dividing signal whose logic level is inverted in response to a change in logic level of an output signal from any one stage of the shift register or logic level of the input signal, in order to divide the clock signal in frequency by a dividing ratio corresponding to the n bits.
    • 分频器电路包括:移位寄存器,其能够存储被配置为与时钟信号同步地顺序移位输入信号的至少n位数据; 脉冲发生电路,被配置为响应于来自移位寄存器的n位输出信号中的来自移位寄存器的级的输出信号的逻辑电平的变化而将输入信号改变为脉冲形式,对应于位 由输入信号移位n位导致的; 以及分频信号生成电路,其被配置为生成分频信号,该分频信号的逻辑电平响应于来自移位寄存器的任何一个级的输出信号或输入信号的逻辑电平的逻辑电平的变化而被反转,以便 将时钟信号的频率除以与n位对应的分频比。
    • 8. 发明申请
    • Digital Data Processing Circuit
    • 数字数据处理电路
    • US20100216417A1
    • 2010-08-26
    • US12391933
    • 2009-02-24
    • Satoshi TeradaMasahiro ObuchiTadahiro Makabe
    • Satoshi TeradaMasahiro ObuchiTadahiro Makabe
    • H04B1/18
    • H04H20/61H04H60/80H04H2201/13
    • A digital data processing circuit includes: an output unit configured to output to an audio signal processing circuit change data for changing a receiving frequency of a FM receiving device as a first frequency to a second frequency in response to an instruction signal providing an instruction to change the receiving frequency to the second frequency, the audio signal processing circuit being a circuit configured to modulate a carrier wave having the first frequency corresponding to setting data with a modulation signal corresponding to an audio signal to be reproduced by the FM receiving device and to the change data, and transmit the modulated carrier wave to the FM receiving device; and a setting unit configured to set the setting data so as to change a frequency of the carrier wave to the second frequency after the output unit outputs the change data to the audio signal processing circuit.
    • 数字数据处理电路包括:输出单元,被配置为响应于提供改变指令的指令信号而输出到音频信号处理电路,用于将FM接收设备的接收频率作为第一频率改变为第二频率 对于第二频率的接收频率,音频信号处理电路是被配置为利用与要由FM接收装置再现的音频信号对应的调制信号来调制具有对应于设定数据的第一频率的载波的电路, 改变数据,并将调制载波传送到FM接收设备; 以及设定单元,被配置为在输出单元将改变数据输出到音频信号处理电路之后,将设置数据设置为将载波的频率改变为第二频率。