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1. 发明授权

US5208831A Network interface system 失效
标题翻译：网络接口系统
公开(公告)号：US5208831A
公开(公告)日：1993-05-04
申请号：US829534
申请日：1992-02-03
申请人： Masaji Ueno , Akihito Nishikawa , Shinichi Iida , Hajime Shiraishi
发明人： Masaji Ueno , Akihito Nishikawa , Shinichi Iida , Hajime Shiraishi
IPC分类号： H04L12/433
CPC分类号： H04L12/433
摘要： It is an object of this invention to provide a novel network interface system which is able to connect automatically to the respective network stations having different data transfer speeds, in order to avoid the above problems. According to this invention, there is provided a detector and a selector in the communication interface to automatically select the appropriate data transfer speed. In the above structure, the speed of communication data transferred by a network is one of two detected by the detector which is able to detect a transfer speed and provide outputs at a first level signal when the transfer speed is at one level and outputs a second level signal when it is at a second level. The selecting means selects the frequency to connect a network station in response to the signal output from the detector. As a result, users need not select the module by themselves, the system automatically select the module.
摘要翻译：本发明的目的是提供一种能够自动连接到具有不同数据传输速度的各个网络站的新型网络接口系统，以避免上述问题。根据本发明，在通信接口中提供了一个检测器和选择器，用于自动选择适当的数据传输速度。在上述结构中，由网络传送的通信数据的速度是检测器检测到的两种速度之一，当传输速度处于一个级别时，能够检测传送速度并提供第一级信号的输出，并输出第二级当它处于第二级时的电平信号。选择装置响应于从检测器输出的信号选择连接网络站的频率。因此，用户不需要自己选择模块，系统自动选择模块。

2. 发明授权

US5767697A Low-voltage output circuit for semiconductor device 失效
标题翻译：半导体器件低压输出电路
公开(公告)号：US5767697A
公开(公告)日：1998-06-16
申请号：US584487
申请日：1996-01-11
申请人： Masaji Ueno , Yasukazu Noine
发明人： Masaji Ueno , Yasukazu Noine
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/094
CPC分类号： H03K19/00315 , H03K19/018521
摘要： A low-voltage output circuit has the first and the second MOS transistors. An input signal is fed to the gate of the first transistor. Either of the source and the drain of the first transistor is supplied with a predetermined potential. The other is connected to an output terminal and generates an output signal. The first transistor raises the output signal to the predetermined potential level in response to the input signal. Either of the source and the drain of the second MOS transistor is connected to the gate of the first transistor. The other is connected to the output terminal. The circuit further includes a device for supplying a bias voltage to a gate of the second transistor so that the first and second transistors remain turned off at different gate bias potentials and the second transistor turns on before the first transistor when the output signal is raised to the predetermined potential level to keep the first transistor remaining turned off. The circuit further includes a device for restricting current flow from the output terminal to the predetermined potential side through the first and second transistors.
摘要翻译：低压输出电路具有第一和第二MOS晶体管。输入信号被馈送到第一晶体管的栅极。第一晶体管的源极和漏极之一被提供预定电位。另一个连接到输出端子并产生输出信号。第一晶体管响应于输入信号将输出信号提高到预定电位电平。第二MOS晶体管的源极和漏极之一连接到第一晶体管的栅极。另一个连接到输出端子。该电路还包括用于向第二晶体管的栅极提供偏置电压的装置，使得第一和第二晶体管在不同的栅极偏置电位下保持截止，并且当输出信号升高到第一晶体管时，第二晶体管导通保持第一晶体管保持关闭的预定电位电平。电路还包括用于限制通过第一和第二晶体管从输出端到预定电位侧的电流的装置。

3. 发明授权

US5408137A Output driver circuit with high breakdown voltage 失效
标题翻译：输出驱动电路具有高击穿电压
公开(公告)号：US5408137A
公开(公告)日：1995-04-18
申请号：US159213
申请日：1993-11-30
申请人： Nobuo Koide , Masaji Ueno
发明人： Nobuo Koide , Masaji Ueno
IPC分类号： H03K17/10 , H03K17/60
CPC分类号： H03K17/102
摘要： A driver circuit suitable for use to secure output characteristics higher than the element breakdown voltage in an output circuit. The driver circuit includes first and second switching elements connected between a first supply voltage and an outward terminal for driving a load, a relaxation voltage applying section for applying a voltage lower than the first supply voltage to a junction point between the first and second switching elements and a back gate of the second switching element, and a control section for turning on the second switching element and then the first switching element in sequence when the driver circuit is turned on, and turning off the first switching element and then the second switching element in sequence when the driver circuit is turned off.
摘要翻译：适用于确保输出特性高于输出电路中的元件击穿电压的驱动电路。驱动器电路包括连接在第一电源电压和用于驱动负载的外部端子之间的第一和第二开关元件，用于将低于第一电源电压的电压施加到第一和第二开关元件之间的接合点的弛豫电压施加部分和第二开关元件的背栅极，以及控制部分，用于当驱动电路导通时依次接通第二开关元件和第一开关元件，并且断开第一开关元件，然后关断第二开关元件当驱动器电路关闭时按顺序。

4. 发明授权

US4996449A Output circuit having high speed operation and low power dissipation 失效
标题翻译：输出电路具有高速运行和低功耗
公开(公告)号：US4996449A
公开(公告)日：1991-02-26
申请号：US380335
申请日：1989-07-17
申请人： Masaji Ueno
发明人： Masaji Ueno
IPC分类号： H03K5/02 , H03K19/00 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/0013 , H03K19/01721
摘要： There is provided an improved output circuit having high speed operation and low power dissipation. The circuit having MOS pull up and pull down transistors, wherein a control signal to the pull down MOS is delayed to discharge parasitic capacitance and to prevent both MOS transistors from being on simultaneously.

5. 发明授权

US09075087B2 Voltage detection circuit, ECU, automobile with ECU 有权
标题翻译：电压检测电路，ECU，带ECU的汽车
公开(公告)号：US09075087B2
公开(公告)日：2015-07-07
申请号：US13419399
申请日：2012-03-13
申请人： Masaji Ueno
发明人： Masaji Ueno
IPC分类号： G01R19/00
CPC分类号： G01R19/0084
摘要： According to an embodiment, the threshold value generation unit generates a setting voltage and converts the setting voltage to a first current. One end of the first resistor is connected to a detection terminal. When a voltage applied to the detection terminal is greater than or equal to a predetermined factor times the voltage of the higher voltage source, the detection unit causes a constant detection terminal input current to flow from the detection terminal to the first resistor. When the voltage at the detection terminal is less than the predetermined factor times the voltage of the higher voltage source, a higher voltage source voltage is outputted to a detection output terminal, while the voltage at the detection terminal is greater than or equal to the predetermined factor times the voltage of the higher voltage source, a lower voltage source voltage is outputted to the detection output terminal.
摘要翻译：根据实施例，阈值生成单元生成设定电压并将设定电压转换为第一电流。第一电阻器的一端连接到检测端子。当检测端子施加的电压大于或等于较高电压源的电压的预定因子时，检测单元使得检测端子输入电流恒定从检测端子流向第一电阻器。当检测端子的电压小于预定因子乘以高电压源的电压时，将较高的电压源电压输出到检测输出端子，而检测端子处的电压大于或等于预定值因子乘以较高电压源的电压，较低的电压源电压被输出到检测输出端子。

6. 发明授权

US08031157B2 Output circuit and liquid crystal display device 失效
标题翻译：输出电路和液晶显示装置
公开(公告)号：US08031157B2
公开(公告)日：2011-10-04
申请号：US11961065
申请日：2007-12-20
申请人： Tomohiro Ando , Masaji Ueno
发明人： Tomohiro Ando , Masaji Ueno
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/2011 , G09G3/3655
摘要： According to an aspect of the present invention, there is provided an output circuit including a first output unit supplying a first voltage, a second output unit supplying a second voltage, a switching unit selectively outputting, to an output end, the first voltage from the first output unit and the second voltage from the second output unit, a detection unit detecting a voltage of the output end, and a control unit controlling one of the first voltage and the second voltage on the basis of the voltage detected by the detection unit.
摘要翻译：根据本发明的一个方面，提供了一种输出电路，包括提供第一电压的第一输出单元，提供第二电压的第二输出单元，选择性地向输出端输出来自第一电压的第一电压的第一电压第一输出单元和来自第二输出单元的第二电压，检测单元检测输出端的电压，以及控制单元，基于由检测单元检测的电压来控制第一电压和第二电压中的一个。

7. 发明授权

US6104218A High breakdown voltage push-pull circuit for semiconductor device 失效
标题翻译：半导体器件的高击穿电压推挽电路
公开(公告)号：US6104218A
公开(公告)日：2000-08-15
申请号：US993022
申请日：1997-12-18
申请人： Masaji Ueno
发明人： Masaji Ueno
IPC分类号： H03K17/10 , H03B1/00 , H03K17/66
CPC分类号： H03K19/00315 , H03K19/01825
摘要： The chip size of the high breakdown voltage push-pull output circuit for the semiconductor device can be reduced by use of only the low breakdown voltage transistor elements. Between the voltage supply terminal HVCC and the ground terminal GND, the control transistor element (Q1) and the voltage transistor element (Q3) are connected in series and stacked vertically. In the same way, the voltage transistor element (Q4) and the control transistor element (Q2) are connected in series and stacked vertically. Further, the output terminal (OUT) is derived from between the voltage transistor element (Q3) and the voltage transistor element (Q4). The supply voltage of 12V supplied through the voltage supply terminal HVCC is divided as voltages of 6V by the bias circuit BI, and then supplied to the bases of the two voltage transistor elements (Q3 and Q4), respectively. When the output is low, the supply voltage of 12V is divided 1/2 by the control transistor element (Q1) and the voltage transistor element (Q3). On the other hand, when the output is high, the supply voltage of 12V is divided 1/2 by the voltage transistor element (Q4) and the control transistor element (Q2). Therefore, it is possible to construct a push-pull circuit with a high breakdown voltage by use of only the low breakdown voltage transistor elements.
摘要翻译：通过仅使用低击穿电压晶体管元件，可以减小用于半导体器件的高击穿电压推挽输出电路的芯片尺寸。在电源端子HVCC和接地端子GND之间，控制晶体管元件（Q1）和电压晶体管元件（Q3）串联连接并垂直堆叠。以相同的方式，电压晶体管元件（Q4）和控制晶体管元件（Q2）串联连接并垂直堆叠。此外，输出端子（OUT）从电压晶体管元件（Q3）和电压晶体管元件（Q4）之间导出。通过电压端子HVCC提供的12V的电源电压被偏置电路BI分压为6V的电压，然后分别提供给两个电压晶体管元件（Q3和Q4）的基极。当输出为低电平时，12V的电源电压由控制晶体管元件（Q1）和电压晶体管元件（Q3）分为+ E，fra 1/2 + EE。另一方面，当输出为高电平时，12V的电源电压由电压晶体管元件（Q4）和控制晶体管元件（Q2）分隔为+ E，fra 1/2 + EE。因此，可以通过仅使用低击穿电压晶体管元件来构造具有高击穿电压的推挽电路。

8. 发明授权

US5136253A Phase comparator having two different phase comparison characteristics 失效
标题翻译：具有两个不同相位比较特性的相位比较器
公开(公告)号：US5136253A
公开(公告)日：1992-08-04
申请号：US581304
申请日：1990-09-12
申请人： Masaji Ueno
发明人： Masaji Ueno
IPC分类号： H03K5/26 , H03D13/00 , H03K7/08 , H03L7/089
CPC分类号： H03D13/004 , H03L7/0891
摘要： A phase comparator has a switching circuit controlled by a switch signal and a phase comparing unit. The switching circuit receives a reference pulse signal having a duty ratio of 50% and a reception data signal having a duty ratio of less than 50%. One of these signals is selected by the switching circuit on the basis of control of the switch signal. The selected signal and an output signal from a voltage-controlled oscillator are supplied to the phase comparing unit. The phase comparing unit compares phases of the two signals. When the phase of the output signal from the voltage-controlled oscillator lags behind the phase of the selected reference pulse signal or reception data signal, the phase comparing unit outputs a first pulse signal, having a width corresponding to a phase difference between the two signals, for advancing the phase of the output signal from the voltage-controlled oscillator. When the phase of the output signal from the voltage-controlled oscillator leads ahead of the phase of the selected reference pulse signal or reception data signal, the phase comparator outputs a second pulse signal, having a width corresponding to a phase difference between the two signals, for delaying the phase of the output signal from the voltage-controlled oscillator.

9. 发明授权

US5017808A BI-MOS logic circuit having a switch circuit for discharging electrical charge accumulated in a parasitic capacitor 失效
标题翻译： BI-MOS逻辑电路具有用于放电积聚在寄生电容器中的电荷的开关电路
公开(公告)号：US5017808A
公开(公告)日：1991-05-21
申请号：US472272
申请日：1990-01-30
申请人： Masaji Ueno , Kumi Ofusa
发明人： Masaji Ueno , Kumi Ofusa
IPC分类号： H03K3/286 , H03K3/356 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/00361 , H03K19/0008 , H03K19/09448
摘要： Disclosed herein is a Bi-MOS logic circuit comprising first and second NPN transistors forming an output buffer; first and second MOS transistors for controlling the NPN transistors when the logic circuit is set to a data-latching mode; and third and fourth MOS transistors for controlling the NPN transistors when the logic circuit is set to a data-inputting mode. The Bi-MOS logic circuit further comprises a switch circuit for discharging a parasitic capacitor located at the node of the series circuit comprised of the first and second MOS transistors.

10. 发明授权

US4841172A Bipolar-MOS logic circuit with high speed operation 失效
标题翻译：具有高速运行的双极MOS逻辑电路
公开(公告)号：US4841172A
公开(公告)日：1989-06-20
申请号：US225495
申请日：1988-07-28
申请人： Masaji Ueno , Hideaki Masuoka
发明人： Masaji Ueno , Hideaki Masuoka
IPC分类号： H03K17/04 , H03K17/66 , H03K19/00 , H03K19/013 , H03K19/017 , H03K19/08 , H03K19/088
CPC分类号： H03K19/0136 , H03K19/0013 , H03K19/01721
摘要： A logic circuit comprises a current control means including first and second MOS transistors for controlling the current to the output circuit and also for controlling the output wave form, in accordance with the input signal and the output signal. When the output signal rises from a low level to a high level, a large current is supplied to the output circuit to get a steep rise. When the output signal is high level, the current to the output circuit becomes small, and the power consumption is reduced.

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