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    • 1. 发明授权
    • Compound semiconductor device and method of making it
    • 复合半导体器件及其制造方法
    • US5412236A
    • 1995-05-02
    • US230873
    • 1994-04-20
    • Masahisa IkeyaTadashi SaitoKazuyuki Inokuchi
    • Masahisa IkeyaTadashi SaitoKazuyuki Inokuchi
    • H01L29/812H01L21/285H01L21/335H01L21/338H01L29/778H01L29/788H01L29/48H01L29/80
    • H01L21/28587H01L29/66462H01L29/7787H01L29/8128
    • In a method of making a semiconductor device, an active layer and a heavily doped cap layer are formed in turn on a semiconductor substrate, a first electrode is formed on the cap layer, a mask of a two-layer structure is formed on the cap layer, with the mask having an insulating film pattern having a non-inverted tapered opening, and a resist pattern having an inverted tapered opening and continuous with the non-inverted tapered opening, these openings being separated by a predetermined distance from the first electrode, and then a recess is formed, by performing an isotropic etching of the heavily doped layer exposed in the openings, with the recess having a bottom surface and a side wall surface rising from an edge of the bottom surface toward the upper edge with a constant radium off curvature. An oblique vapor deposition is then performed to form a second electrode to cover the bottom surface and the part of the side wall surface.
    • 在制造半导体器件的方法中,依次在半导体衬底上形成有源层和重掺杂覆盖层,在覆盖层上形成第一电极,在盖上形成两层结构的掩模 层,其中掩模具有具有非倒锥形开口的绝缘膜图案和具有倒锥形开口并与非倒锥形开口连续的抗蚀剂图案,这些开口与第一电极分开预定距离, 然后通过对在开口中暴露的重掺杂层进行各向同性蚀刻来形成凹部,其中凹部具有底表面和侧壁表面,其从底表面的边缘朝向上边缘以恒定的镭 关闭曲率。 然后进行倾斜气相沉积以形成覆盖底壁表面和侧壁表面的一部分的第二电极。
    • 6. 发明授权
    • Field effect transistor gate bias voltage application circuit and
semiconductor apparatus having field effect transistor gate bias
voltage application circuit
    • 场效应晶体管栅极偏置电压施加电路和具有场效应晶体管栅极偏置电压施加电路的半导体装置
    • US6087888A
    • 2000-07-11
    • US195659
    • 1998-11-18
    • Kazuyuki Inokuchi
    • Kazuyuki Inokuchi
    • H03F1/30H03K17/08H03K17/0812H03K17/14H01L35/00H03K17/687
    • H03K17/08122H03K17/145H03K2017/0806
    • FET gate bias voltage application circuits and semiconductor apparatuses in which such a FET gate bias voltage application circuit is installed compensate for adverse effects caused by changes in the surrounding temperature. A temperature compensation FET is installed in a FET gate bias voltage application circuit in which a divided voltage is applied to the gate of a controlled FET from a first intermediate point of a resistance type potential dividing circuit to which a direct current voltage is applied. This temperature compensation FET becomes conductive at a gate voltage higher than the gate voltage of the controlled FET. A voltage divided at the first intermediate point is applied to the gate of this temperature compensation FET. The drain of this temperature compensation FET is connected to a second intermediate point at which the electric potential is higher than the electric potential at the first intermediate point. The source of this temperature compensation FET is grounded. This temperature compensation FET remains non-conductive when the gate-drain current of the controlled FET is at a low level. This temperature compensation FET becomes conductive when the gate-drain current of the controlled FET increases to a high level to cause a drain-source current to flow through this temperature compensation FET. As a result, the amount of voltage drop increases at a region in which the electric potential is higher than the electric potential at the second intermediate point of the resistance type potential dividing circuit. This causes the electric potentials at the first and second intermediate points, respectively, to be shifted in the negative direction.
    • 其中安装有这种FET栅极偏置电压施加电路的FET栅极偏置电压施加电路和半导体装置补偿由周围温度的变化引起的不利影响。 温度补偿FET安装在FET栅极偏置电压施加电路中,其中从施加有直流电压的电阻型分压电路的第一中间点向受控FET的栅极施加分压。 该温度补偿FET在高于受控FET的栅极电压的栅极电压下变为导通。 在第一中间点分压的电压被施加到该温度补偿FET的栅极。 该温度补偿FET的漏极连接到电位高于第一中间点的电位的第二中间点。 该温度补偿FET的源极接地。 当受控FET的栅极 - 漏极电流处于低电平时,该温度补偿FET保持不导通。 当受控FET的栅极 - 漏极电流增加到高电平以使漏极 - 源极电流流过该温度补偿FET时,该温度补偿FET变为导通。 结果,在电位高于电阻型电位分压电路的第二中间点的电位的区域,电压降的量增加。 这使得分别在第一和第二中间点处的电位沿负方向偏移。