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1. 发明授权

US5412236A Compound semiconductor device and method of making it 失效
标题翻译：复合半导体器件及其制造方法
公开(公告)号：US5412236A
公开(公告)日：1995-05-02
申请号：US230873
申请日：1994-04-20
申请人： Masahisa Ikeya , Tadashi Saito , Kazuyuki Inokuchi
发明人： Masahisa Ikeya , Tadashi Saito , Kazuyuki Inokuchi
IPC分类号： H01L29/812 , H01L21/285 , H01L21/335 , H01L21/338 , H01L29/778 , H01L29/788 , H01L29/48 , H01L29/80
CPC分类号： H01L21/28587 , H01L29/66462 , H01L29/7787 , H01L29/8128
摘要： In a method of making a semiconductor device, an active layer and a heavily doped cap layer are formed in turn on a semiconductor substrate, a first electrode is formed on the cap layer, a mask of a two-layer structure is formed on the cap layer, with the mask having an insulating film pattern having a non-inverted tapered opening, and a resist pattern having an inverted tapered opening and continuous with the non-inverted tapered opening, these openings being separated by a predetermined distance from the first electrode, and then a recess is formed, by performing an isotropic etching of the heavily doped layer exposed in the openings, with the recess having a bottom surface and a side wall surface rising from an edge of the bottom surface toward the upper edge with a constant radium off curvature. An oblique vapor deposition is then performed to form a second electrode to cover the bottom surface and the part of the side wall surface.
摘要翻译：在制造半导体器件的方法中，依次在半导体衬底上形成有源层和重掺杂覆盖层，在覆盖层上形成第一电极，在盖上形成两层结构的掩模层，其中掩模具有具有非倒锥形开口的绝缘膜图案和具有倒锥形开口并与非倒锥形开口连续的抗蚀剂图案，这些开口与第一电极分开预定距离，然后通过对在开口中暴露的重掺杂层进行各向同性蚀刻来形成凹部，其中凹部具有底表面和侧壁表面，其从底表面的边缘朝向上边缘以恒定的镭关闭曲率。然后进行倾斜气相沉积以形成覆盖底壁表面和侧壁表面的一部分的第二电极。

2. 发明授权

US06251696B1 Method of forming integrated circuit with evaluation contacts electrically connected by forming via holes through the chip, and bonding the chip with a substrate 有权
标题翻译：通过在芯片上形成通孔并将芯片与衬底接合而形成具有电连接的评估触点的集成电路的方法
公开(公告)号：US06251696B1
公开(公告)日：2001-06-26
申请号：US09426184
申请日：1999-10-25
申请人： Masahisa Ikeya , Kazuyuki Inokuchi
发明人： Masahisa Ikeya , Kazuyuki Inokuchi
IPC分类号： H01L2166
CPC分类号： H01L22/34 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an integrated circuit of which a bonding condition can be evaluated simply is provided. Two external connecting electrodes are provided on the surface, via holes are formed below them, and conductive portions are formed in the via holes. Then, a first metal film is formed on a rear face of a chip and a second metal film is formed on a surface of a ceramic substrate, and then both of them are made contact and heated so as to bond the chip and the ceramic substrate. Further, when the first metal film is formed, a slit portion which no first metal film exists is provided. When the bonding condition is evaluated, a resistance between two external connecting electrodes is measured.
摘要翻译：提供一种制造可以简单地评估接合条件的集成电路的方法。在其表面上设置有两个外部连接电极，在其下方形成通孔，并且在通孔中形成导电部分。然后，在芯片的背面形成第一金属膜，在陶瓷基板的表面上形成第二金属膜，然后将它们接触加热，从而将芯片和陶瓷基板。此外，当形成第一金属膜时，提供不存在第一金属膜的狭缝部分。当评估接合条件时，测量两个外部连接电极之间的电阻。

3. 发明授权

US06423559B2 Integrated circuit and fabricating method and evaluating method of integrated circuit 有权
标题翻译：集成电路及其与衬底的集成电路接合的制造方法和评估方法
公开(公告)号：US06423559B2
公开(公告)日：2002-07-23
申请号：US09734742
申请日：2000-12-13
申请人： Masahisa Ikeya , Kazuyuki Inokuchi
发明人： Masahisa Ikeya , Kazuyuki Inokuchi
IPC分类号： G01R3126
CPC分类号： H01L22/34 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an integrated circuit of which a bonding condition can be evaluated simply is provided. Two external connecting electrodes are provided on the surface, via holes are formed below them, and conductive portions are formed in the via holes. Then, a first metal film is formed on a rear face of a chip and a second metal film is formed on a surface of a ceramic substrate, and then both of them are made contact and heated so as to bond the chip and the ceramic substrate. Further, when the first metal film is formed, a slit portion which no first metal film exists is provided. When the bonding condition is evaluated, a resistance between two external connecting electrodes is measured.
摘要翻译：提供一种制造可以简单地评估接合条件的集成电路的方法。在其表面上设置有两个外部连接电极，在其下方形成通孔，并且在通孔中形成导电部分。然后，在芯片的背面形成第一金属膜，在陶瓷基板的表面上形成第二金属膜，然后将它们接触加热，从而将芯片和陶瓷基板。此外，当形成第一金属膜时，提供不存在第一金属膜的狭缝部分。当评估接合条件时，测量两个外部连接电极之间的电阻。

4. 发明授权

US5994716A Integrated circuit and fabricating method and evaluating method of integrated circuit 失效
标题翻译：集成电路的集成电路及其制作方法及评估方法
公开(公告)号：US5994716A
公开(公告)日：1999-11-30
申请号：US864860
申请日：1997-05-29
申请人： Masahisa Ikeya , Kazuyuki Inokuchi
发明人： Masahisa Ikeya , Kazuyuki Inokuchi
IPC分类号： G01R31/26 , H01L21/60 , H01L21/66 , H01L23/48 , H01L23/544 , H01L23/58 , H01L23/04
CPC分类号： H01L22/34 , H01L23/481 , H01L2924/0002
摘要： A method of fabricating an integrated circuit of which a bonding condition can be evaluated simply is provided. Two external connecting electrodes are provided on the surface, via holes are formed below them, and conductive portions are formed in the via holes. Then, a first metal film is formed on a rear face of a chip and a second metal film is formed on a surface of a ceramic substrate, and then both of them are made contact and heated so as to bond the chip and the ceramic substrate. Further, when the first metal film is formed, a slit portion which no first metal film exists is provided. When the bonding condition is evaluated, a resistance between two external connecting electrodes is measured.
摘要翻译：提供一种制造可以简单地评估接合条件的集成电路的方法。在其表面上设置有两个外部连接电极，在其下方形成通孔，并且在通孔中形成导电部分。然后，在芯片的背面形成第一金属膜，在陶瓷基板的表面上形成第二金属膜，然后将它们接触加热，从而将芯片和陶瓷基板。此外，当形成第一金属膜时，提供不存在第一金属膜的狭缝部分。当评估接合条件时，测量两个外部连接电极之间的电阻。

5. 发明授权

US06440846B1 Method for forming semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US06440846B1
公开(公告)日：2002-08-27
申请号：US09584729
申请日：2000-06-01
申请人： Masahisa Ikeya
发明人： Masahisa Ikeya
IPC分类号： H01L214763
CPC分类号： H01L21/76898 , H01L21/0272
摘要： In a method for forming a semiconductor device, when polishing the wafer, the photo-resin so as to cure with ultraviolet is buried. Then, after polishing and forming the back side electrode, the photo-resin is removed by organic solvent. Accordingly, the method can improve reliability of bonding and simplify process flow without decreasing electrical characteristics.
摘要翻译：在形成半导体器件的方法中，当研磨晶片时，掩埋光固化物以使紫外线固化。然后，在抛光和形成背面电极之后，通过有机溶剂去除光树脂。因此，该方法可以提高接合的可靠性并简化工艺流程，而不会降低电气特性。

6. 发明授权

US06919541B2 Apparatus for preventing rapid temperature variation during wafer processing 有权
标题翻译：用于防止晶片加工过程中温度快速变化的装置
公开(公告)号：US06919541B2
公开(公告)日：2005-07-19
申请号：US10135444
申请日：2002-05-01
申请人： Masahisa Ikeya
发明人： Masahisa Ikeya
IPC分类号： G05D23/00 , H01L21/00 , H01L21/677 , H05B3/68 , C23C16/00
CPC分类号： H01L21/67109 , H01L21/67742 , H01L21/67745
摘要： An apparatus for fabricating a semiconductor device, whereby a semiconductor wafer is thermally treated with a wafer treatment device. The semiconductor wafer is delivered with a conveyer to the wafer treatment device. The temperature of the conveyer is controlled to have an optimum temperature by an arm heater and an arm cooler.
摘要翻译：一种用于制造半导体器件的装置，由此利用晶片处理装置对半导体晶片进行热处理。将半导体晶片与输送机一起输送到晶片处理装置。通过臂式加热器和臂式冷却器将输送机的温度控制为具有最佳温度。

7. 发明授权

US06867120B2 Method of fabricating a semiconductor device with a gold conductive layer and organic insulating layer 有权
标题翻译：制造具有金导电层和有机绝缘层的半导体器件的方法
公开(公告)号：US06867120B2
公开(公告)日：2005-03-15
申请号：US10353028
申请日：2003-01-29
申请人： Takehiko Okajima , Masahisa Ikeya
发明人： Takehiko Okajima , Masahisa Ikeya
IPC分类号： H01L21/28 , H01L21/306 , H01L21/312 , H01L21/3205 , H01L21/3213 , H01L21/44 , H01L21/768 , H01L23/52 , H01L23/522
CPC分类号： H01L21/3125 , H01L21/02052 , H01L21/02126 , H01L21/02211 , H01L21/02307 , H01L21/32131 , H01L21/76804 , H01L21/76828 , H01L21/76834 , Y10S438/906
摘要： In a semiconductor device, particles are removed from the surface of a gold conductive layer before an intermediate insulating layer of an amino silane compound is formed. An organic insulating layer is formed on the intermediate insulating layer. As a result, adhesion strength between the conductive layer and the intermediate insulating layer can be improved.
摘要翻译：在半导体器件中，在形成氨基硅烷化合物的中间绝缘层之前，从金导电层的表面除去颗粒。在中间绝缘层上形成有机绝缘层。结果，可以提高导电层和中间绝缘层之间的粘附强度。

8. 发明授权

US06413888B1 Method and apparatus for preventing rapid temperature variation of wafers during processing 有权
标题翻译：用于在处理期间防止晶片快速温度变化的方法和装置
公开(公告)号：US06413888B1
公开(公告)日：2002-07-02
申请号：US09206235
申请日：1998-12-07
申请人： Masahisa Ikeya
发明人： Masahisa Ikeya
IPC分类号： H01L21324
CPC分类号： H01L21/67109 , H01L21/67742 , H01L21/67745
摘要： In a method for fabricating a semiconductor device, a semiconductor wafer is thermally treated with a wafer treatment device, such as in a diffustion process. The semiconductor wafer is deliverd to the treatment device using a conveyor system. The conveyor system is operated in an arrangement consisting of at least two connected armatures and is operated with both heating and cooling elements. The heating and cooling element are implemented for optimal temperture control of the connected conveyor arms with respect to increase throughout while avoiding thermal shock.
摘要翻译：在制造半导体器件的方法中，半导体晶片通过晶圆处理装置进行热处理，例如在扩散工艺中。半导体晶片使用输送系统输送到处理装置。传送系统以由至少两个连接的电枢组成的布置操作，并且与加热和冷却元件一起操作。实施加热和冷却元件以相对于全部增加而避免热冲击来实现连接的传送臂的最佳温度控制。

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