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1. 发明授权

US06841993B2 Bearing provided with rotation sensor and motor employing the same 有权
标题翻译：轴承设有旋转传感器和采用该传感器的电机
公开(公告)号：US06841993B2
公开(公告)日：2005-01-11
申请号：US10820795
申请日：2004-04-09
申请人： Kenichi Iwamoto , Takashi Koike , Motoharu Niki , Kazuyuki Inokuchi
发明人： Kenichi Iwamoto , Takashi Koike , Motoharu Niki , Kazuyuki Inokuchi
IPC分类号： G01P3/44
CPC分类号： G01P3/443 , F16C19/06 , F16C41/007
摘要： A bearing provided with a rotation sensor comprises an outer ring, an inner ring and rolling elements, and a magnetic ring is engaged with the inner diametral surface of the outer ring. Thus, a highly reliable bearing provided with a rotation sensor exerting no bad influence on a magnetic sensor can be provided.
摘要翻译：设置有旋转传感器的轴承包括外圈，内圈和滚动元件，并且磁环与外圈的内径表面接合。因此，可以提供设置有对磁传感器没有不良影响的旋转传感器的高度可靠的轴承。

2. 发明授权

US06666784B1 Piston rod piston detector, autotensioner and belt tension adjuster 失效
标题翻译：活塞杆活塞检测器，自动张紧器和皮带张力调节器
公开(公告)号：US06666784B1
公开(公告)日：2003-12-23
申请号：US09679809
申请日：2000-10-05
申请人： Kenichi Iwamoto , Takashi Koike , Kazuyuki Inokuchi , Motoharu Niki
发明人： Kenichi Iwamoto , Takashi Koike , Kazuyuki Inokuchi , Motoharu Niki
IPC分类号： F16H708
CPC分类号： G01B7/02 , F01L1/024 , F01L9/04 , F01L2820/045 , F15B15/2861 , F16H7/0836 , F16H2007/0806 , F16H2007/081 , F16H2007/0812 , F16H2007/0861 , G01B7/003 , G01D5/2013 , G01D5/2046 , Y10T137/8242
摘要： A piston rod position detecting mechanism is proposed which can detect continuously or in a multiple-point manner that the piston rod position has changed due to increase or decrease in the protruding amount of the piston rod due to aging. The protruding amount from a cylinder end wall is detected by a position detecting mechanism comprising a detecting coil housed in a bobbin provided at the cylinder end, a flange portion formed on the piston rod, and a coil spring. Also, an autotensioner and an electromagnetic valve with such a position detector are proposed. Further, a belt tension adjusting device is provided with a detector for detecting the position of a tension pulley which is pivotable with increase or decrease in the belt tension.
摘要翻译：提出一种活塞杆位置检测机构，其可以连续或多点地检测活塞杆位置由于老化引起的活塞杆突出量的增加或减少而发生变化。通过位置检测机构检测来自气缸端壁的突出量，位置检测机构包括容纳在设置在气缸端的筒管中的检测线圈，形成在活塞杆上的凸缘部分和螺旋弹簧。此外，提出了一种具有这种位置检测器的自动张紧器和电磁阀。此外，皮带张力调节装置设置有用于检测张力皮带轮的位置的检测器，所述张力皮带轮可以随皮带张力的增加或减小而转动。

3. 发明授权

US07081059B2 Piston rod position detector, autotensioner and belt tension adjuster 失效
标题翻译：活塞杆位置检测器，自动张紧器和皮带张力调节器
公开(公告)号：US07081059B2
公开(公告)日：2006-07-25
申请号：US10699788
申请日：2003-11-04
申请人： Kenichi Iwamoto , Takashi Koike , Kazuyuki Inokuchi , Motoharu Niki
发明人： Kenichi Iwamoto , Takashi Koike , Kazuyuki Inokuchi , Motoharu Niki
IPC分类号： F16H7/08 , G08B1/00 , G01B7/00
CPC分类号： G01B7/02 , F01L1/024 , F01L9/04 , F01L2820/045 , F15B15/2861 , F16H7/0836 , F16H2007/0806 , F16H2007/081 , F16H2007/0812 , F16H2007/0861 , G01B7/003 , G01D5/2013 , G01D5/2046 , Y10T137/8242
摘要： A piston rod position detecting mechanism is proposed which can detect continuously or in a multiple-point manner that the piston rod position has changed due to increase or decrease in the protruding amount of the piston rod due to aging. The protruding amount from a cylinder end wall is detected by a position detecting mechanism comprising a detecting coil housed in a bobbin provided at the cylinder end, a flange portion formed on the piston rod, and a coil spring. Also, an autotensioner and an electromagnetic valve with such a position detector are proposed. Further, a belt tension adjusting device is provided with a detector for detecting the position of a tension pulley which is pivotable with increase or decrease in the belt tension.
摘要翻译：提出一种活塞杆位置检测机构，其可以连续或多点地检测活塞杆位置由于老化引起的活塞杆突出量的增加或减少而发生变化。通过位置检测机构检测来自气缸端壁的突出量，位置检测机构包括容纳在设置在气缸端的筒管中的检测线圈，形成在活塞杆上的凸缘部分和螺旋弹簧。此外，提出了一种具有这种位置检测器的自动张紧器和电磁阀。此外，皮带张力调节装置设置有用于检测张力皮带轮的位置的检测器，所述张力皮带轮可以随皮带张力的增加或减小而转动。

4. 发明授权

US06570751B2 Magnetic encoder, wheel bearing and method of manufacturing magnetic encoder 有权
标题翻译：磁编码器，车轮轴承及磁编码器制造方法
公开(公告)号：US06570751B2
公开(公告)日：2003-05-27
申请号：US09785468
申请日：2001-02-20
申请人： Kenichi Iwamoto , Takashi Koike , Kazuyuki Inokuchi
发明人： Kenichi Iwamoto , Takashi Koike , Kazuyuki Inokuchi
IPC分类号： G01P3487
CPC分类号： G01P3/443 , F16C19/184 , F16C41/007 , F16C2326/02 , G01P3/487 , H01F13/003 , Y10T29/49004
摘要： A magnetization yoke having an exciting coil wound thereon is arranged to hold a magnetic member and a metal ring so that a magnetic flux passes through and magnetizes the magnetic member in the portion held by the magnetization yoke for successively magnetizing the magnetic member along the circumferential direction thereby multipolarly magnetizing the magnetic member in the circumferential direction. Thus, a magnetic encoder having large magnetization strength and a small magnetization pitch error, a wheel bearing employing the same and a method of manufacturing a magnetic encoder can be obtained.
摘要翻译：具有缠绕在其上的励磁线圈的磁轭被布置成保持磁性构件和金属环，使得磁通量通过并磁化由磁轭固定的部分中的磁性构件，以沿着圆周方向依次磁化磁性构件从而在圆周方向上多次磁化磁性部件。因此，可以获得具有高磁化强度和小磁化倾斜误差的磁编码器，使用该磁编码器的车轮轴承和制造磁编码器的方法。

5. 发明授权

US6087888A Field effect transistor gate bias voltage application circuit and semiconductor apparatus having field effect transistor gate bias voltage application circuit 失效
标题翻译：场效应晶体管栅极偏置电压施加电路和具有场效应晶体管栅极偏置电压施加电路的半导体装置
公开(公告)号：US6087888A
公开(公告)日：2000-07-11
申请号：US195659
申请日：1998-11-18
申请人： Kazuyuki Inokuchi
发明人： Kazuyuki Inokuchi
IPC分类号： H03F1/30 , H03K17/08 , H03K17/0812 , H03K17/14 , H01L35/00 , H03K17/687
CPC分类号： H03K17/08122 , H03K17/145 , H03K2017/0806
摘要： FET gate bias voltage application circuits and semiconductor apparatuses in which such a FET gate bias voltage application circuit is installed compensate for adverse effects caused by changes in the surrounding temperature. A temperature compensation FET is installed in a FET gate bias voltage application circuit in which a divided voltage is applied to the gate of a controlled FET from a first intermediate point of a resistance type potential dividing circuit to which a direct current voltage is applied. This temperature compensation FET becomes conductive at a gate voltage higher than the gate voltage of the controlled FET. A voltage divided at the first intermediate point is applied to the gate of this temperature compensation FET. The drain of this temperature compensation FET is connected to a second intermediate point at which the electric potential is higher than the electric potential at the first intermediate point. The source of this temperature compensation FET is grounded. This temperature compensation FET remains non-conductive when the gate-drain current of the controlled FET is at a low level. This temperature compensation FET becomes conductive when the gate-drain current of the controlled FET increases to a high level to cause a drain-source current to flow through this temperature compensation FET. As a result, the amount of voltage drop increases at a region in which the electric potential is higher than the electric potential at the second intermediate point of the resistance type potential dividing circuit. This causes the electric potentials at the first and second intermediate points, respectively, to be shifted in the negative direction.
摘要翻译：其中安装有这种FET栅极偏置电压施加电路的FET栅极偏置电压施加电路和半导体装置补偿由周围温度的变化引起的不利影响。温度补偿FET安装在FET栅极偏置电压施加电路中，其中从施加有直流电压的电阻型分压电路的第一中间点向受控FET的栅极施加分压。该温度补偿FET在高于受控FET的栅极电压的栅极电压下变为导通。在第一中间点分压的电压被施加到该温度补偿FET的栅极。该温度补偿FET的漏极连接到电位高于第一中间点的电位的第二中间点。该温度补偿FET的源极接地。当受控FET的栅极 - 漏极电流处于低电平时，该温度补偿FET保持不导通。当受控FET的栅极 - 漏极电流增加到高电平以使漏极 - 源极电流流过该温度补偿FET时，该温度补偿FET变为导通。结果，在电位高于电阻型电位分压电路的第二中间点的电位的区域，电压降的量增加。这使得分别在第一和第二中间点处的电位沿负方向偏移。

6. 发明授权

US5872369A Solid-state antenna switch and field-effect transistor 失效
标题翻译：固态天线开关和场效晶体管
公开(公告)号：US5872369A
公开(公告)日：1999-02-16
申请号：US791845
申请日：1997-01-30
申请人： Kazuyuki Inokuchi
发明人： Kazuyuki Inokuchi
IPC分类号： H01L21/822 , H01L21/338 , H01L27/04 , H01L29/812 , H01Q1/00 , H01Q3/00 , H01Q23/00 , H03K17/687 , H04B1/40 , H04B1/48
CPC分类号： H01L29/402 , H01L29/8124 , H03K17/687 , H04B1/48
摘要： A field-effect transistor has a covering electrode overlying at least part of the transistor's channel. The covering electrode is formed on an insulating layer that covers the source, gate, and drain of the transistor. One voltage is applied to the covering electrode when the field-effect transistor is switched on. Another voltage is applied when the field-effect transistor is switched off, creating an electric field that hinders current flow in the channel. In an antenna switch, this type of transistor couples an antenna to a receiving circuit, and another transistor couples the antenna to a transmitting circuit.
摘要翻译：场效应晶体管具有覆盖晶体管通道的至少一部分的覆盖电极。覆盖电极形成在覆盖晶体管的源极，栅极和漏极的绝缘层上。当场效晶体管导通时，一个电压施加到覆盖电极。当场效应晶体管关断时施加另一电压，产生阻碍通道中的电流的电场。在天线开关中，这种类型的晶体管将天线耦合到接收电路，而另一晶体管将天线耦合到发射电路。

7. 发明授权

US06294801B1 Semiconductor device with Schottky layer 有权
标题翻译：具肖特基层的半导体器件
公开(公告)号：US06294801B1
公开(公告)日：2001-09-25
申请号：US09296496
申请日：1999-04-22
申请人： Kazuyuki Inokuchi , Seiichi Takahashi , Shinichi Hoshi , Tadashi Saito , Nobusuke Yamamoto , Yuko Itoh , Nobumasa Higemoto
发明人： Kazuyuki Inokuchi , Seiichi Takahashi , Shinichi Hoshi , Tadashi Saito , Nobusuke Yamamoto , Yuko Itoh , Nobumasa Higemoto
IPC分类号： H01L31072
CPC分类号： H01L29/66462 , H01L29/42316 , H01L29/7785
摘要： A semiconductor device includes a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure. The Schottky electrode has a lower portion that penetrates through the cap layer and reaches the Schottky layer, and has an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.
摘要翻译：半导体器件包括肖特基层，覆盖肖特基层表面的覆盖层和双层结构的肖特基电极。肖特基电极具有穿过盖层并到达肖特基层的下部，并且具有大于截面积的下部的上部，并且覆盖在盖层上。利用这种结构，不可能发生表面缺陷，从而可以制造高可靠性的半导体器件。

8. 发明授权

US5412236A Compound semiconductor device and method of making it 失效
标题翻译：复合半导体器件及其制造方法
公开(公告)号：US5412236A
公开(公告)日：1995-05-02
申请号：US230873
申请日：1994-04-20
申请人： Masahisa Ikeya , Tadashi Saito , Kazuyuki Inokuchi
发明人： Masahisa Ikeya , Tadashi Saito , Kazuyuki Inokuchi
IPC分类号： H01L29/812 , H01L21/285 , H01L21/335 , H01L21/338 , H01L29/778 , H01L29/788 , H01L29/48 , H01L29/80
CPC分类号： H01L21/28587 , H01L29/66462 , H01L29/7787 , H01L29/8128
摘要： In a method of making a semiconductor device, an active layer and a heavily doped cap layer are formed in turn on a semiconductor substrate, a first electrode is formed on the cap layer, a mask of a two-layer structure is formed on the cap layer, with the mask having an insulating film pattern having a non-inverted tapered opening, and a resist pattern having an inverted tapered opening and continuous with the non-inverted tapered opening, these openings being separated by a predetermined distance from the first electrode, and then a recess is formed, by performing an isotropic etching of the heavily doped layer exposed in the openings, with the recess having a bottom surface and a side wall surface rising from an edge of the bottom surface toward the upper edge with a constant radium off curvature. An oblique vapor deposition is then performed to form a second electrode to cover the bottom surface and the part of the side wall surface.
摘要翻译：在制造半导体器件的方法中，依次在半导体衬底上形成有源层和重掺杂覆盖层，在覆盖层上形成第一电极，在盖上形成两层结构的掩模层，其中掩模具有具有非倒锥形开口的绝缘膜图案和具有倒锥形开口并与非倒锥形开口连续的抗蚀剂图案，这些开口与第一电极分开预定距离，然后通过对在开口中暴露的重掺杂层进行各向同性蚀刻来形成凹部，其中凹部具有底表面和侧壁表面，其从底表面的边缘朝向上边缘以恒定的镭关闭曲率。然后进行倾斜气相沉积以形成覆盖底壁表面和侧壁表面的一部分的第二电极。

9. 发明授权

US06537865B2 Semiconductor device and process of fabricating same 失效
标题翻译：半导体器件及其制造工艺
公开(公告)号：US06537865B2
公开(公告)日：2003-03-25
申请号：US09930136
申请日：2001-08-16
申请人： Kazuyuki Inokuchi , Seiichi Takahashi , Shinichi Hoshi , Tadashi Saito , Nobusuke Yamamoto , Yuko Itoh , Nobumasa Higemoto
发明人： Kazuyuki Inokuchi , Seiichi Takahashi , Shinichi Hoshi , Tadashi Saito , Nobusuke Yamamoto , Yuko Itoh , Nobumasa Higemoto
IPC分类号： H01L21338
CPC分类号： H01L29/66462 , H01L29/42316 , H01L29/7785
摘要： A semiconductor device fabrication process includes forming a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure having a lower portion that penetrates through the cap layer and reaches the Schottky layer, and having an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.
摘要翻译：半导体器件制造工艺包括形成肖特基层，覆盖肖特基层表面的覆盖层和具有穿透盖层并到达肖特基层的下部的二级结构的肖特基电极，并且具有在上部比横截面积的下部大的部分，覆盖在盖层上。利用这种结构，不可能发生表面缺陷，从而可以制造高可靠性的半导体器件。

10. 发明授权

US06251696B1 Method of forming integrated circuit with evaluation contacts electrically connected by forming via holes through the chip, and bonding the chip with a substrate 有权
标题翻译：通过在芯片上形成通孔并将芯片与衬底接合而形成具有电连接的评估触点的集成电路的方法
公开(公告)号：US06251696B1
公开(公告)日：2001-06-26
申请号：US09426184
申请日：1999-10-25
申请人： Masahisa Ikeya , Kazuyuki Inokuchi
发明人： Masahisa Ikeya , Kazuyuki Inokuchi
IPC分类号： H01L2166
CPC分类号： H01L22/34 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating an integrated circuit of which a bonding condition can be evaluated simply is provided. Two external connecting electrodes are provided on the surface, via holes are formed below them, and conductive portions are formed in the via holes. Then, a first metal film is formed on a rear face of a chip and a second metal film is formed on a surface of a ceramic substrate, and then both of them are made contact and heated so as to bond the chip and the ceramic substrate. Further, when the first metal film is formed, a slit portion which no first metal film exists is provided. When the bonding condition is evaluated, a resistance between two external connecting electrodes is measured.
摘要翻译：提供一种制造可以简单地评估接合条件的集成电路的方法。在其表面上设置有两个外部连接电极，在其下方形成通孔，并且在通孔中形成导电部分。然后，在芯片的背面形成第一金属膜，在陶瓷基板的表面上形成第二金属膜，然后将它们接触加热，从而将芯片和陶瓷基板。此外，当形成第一金属膜时，提供不存在第一金属膜的狭缝部分。当评估接合条件时，测量两个外部连接电极之间的电阻。

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