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1. 发明授权

US08749068B2 Mounting method and mounting device 失效
标题翻译：安装方法和安装装置
公开(公告)号：US08749068B2
公开(公告)日：2014-06-10
申请号：US13519243
申请日：2010-12-24
申请人： Michikazu Nakamura , Masahiko Sugiyama , Dai Shinozaki , Naoki Akiyama
发明人： Michikazu Nakamura , Masahiko Sugiyama , Dai Shinozaki , Naoki Akiyama
IPC分类号： H01L23/48
CPC分类号： H01L24/83 , H01L21/67132 , H01L21/67144 , H01L21/6835 , H01L24/27 , H01L24/29 , H01L24/743 , H01L24/75 , H01L24/97 , H01L2221/68313 , H01L2224/27312 , H01L2224/7565 , H01L2224/83002 , H01L2224/83143 , H01L2224/83192 , H01L2224/83193 , H01L2224/838 , H01L2224/92 , H01L2224/97 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/14 , H01L2924/15788 , H01L2224/27 , H01L2224/83 , H01L2924/00
摘要： A mounting method of sequentially mounting elements on a substrate includes a mounting process of mounting one element, which is taken out by a take-out part from an accommodating part in which the elements are accommodated, on a first contact region of the surface of the substrate where a liquid is coated. The method further includes a coating process of coating a liquid, by a coating part movably provided together with the take-out part, on a contact region of the surface of the substrate different from the first contact region when the one element is mounted on the first region.
摘要翻译：将元件依次安装在基板上的安装方法包括安装过程，该安装方法将一个元件安装在一个元件的表面的第一接触区域上，该元件由取出部分从容纳元件被容纳的容纳部分中取出，衬底，其中涂布液体。该方法还包括一种涂覆方法，该涂覆方法通过可移动地与取出部分一起设置的涂层部分涂覆在与该第一接触区域不同的第一接触区域的基板的表面的接触区域上，第一区。

2. 发明申请

US20120292775A1 MOUNTING METHOD AND MOUNTING DEVICE 失效
标题翻译：安装方法和安装设备
公开(公告)号：US20120292775A1
公开(公告)日：2012-11-22
申请号：US13519243
申请日：2010-12-24
申请人： Michikazu Nakamura , Masahiko Sugiyama , Dai Shinozaki , Naoki Akiyama
发明人： Michikazu Nakamura , Masahiko Sugiyama , Dai Shinozaki , Naoki Akiyama
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L24/83 , H01L21/67132 , H01L21/67144 , H01L21/6835 , H01L24/27 , H01L24/29 , H01L24/743 , H01L24/75 , H01L24/97 , H01L2221/68313 , H01L2224/27312 , H01L2224/7565 , H01L2224/83002 , H01L2224/83143 , H01L2224/83192 , H01L2224/83193 , H01L2224/838 , H01L2224/92 , H01L2224/97 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/14 , H01L2924/15788 , H01L2224/27 , H01L2224/83 , H01L2924/00
摘要： A mounting method of sequentially mounting elements on a substrate includes a mounting process of mounting one element, which is taken out by a take-out part from an accommodating part in which the elements are accommodated, on a first contact region of the surface of the substrate where a liquid is coated. The method further includes a coating process of coating a liquid, by a coating part movably provided together with the take-out part, on a contact region of the surface of the substrate different from the first contact region when the one element is mounted on the first region.
摘要翻译：将元件依次安装在基板上的安装方法包括安装过程，该安装方法将一个元件安装在一个元件的表面的第一接触区域上，该元件由取出部分从容纳元件被容纳的容纳部分中取出，衬底，其中涂布液体。该方法还包括一种涂覆方法，该涂覆方法通过可移动地与取出部分一起设置的涂层部分涂覆在与该第一接触区域不同的第一接触区域的基板的表面的接触区域上，第一区。

3. 发明申请

US20120291950A1 MOUNTING METHOD AND MOUNTING DEVICE 审中-公开
标题翻译：安装方法和安装设备
公开(公告)号：US20120291950A1
公开(公告)日：2012-11-22
申请号：US13519237
申请日：2010-12-24
申请人： Masahiko Sugiyama , Michikazu Nakamura , Dai Shinozaki , Naoki Akiyama
发明人： Masahiko Sugiyama , Michikazu Nakamura , Dai Shinozaki , Naoki Akiyama
IPC分类号： B32B38/00 , B32B38/18
CPC分类号： H01L21/6835 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/97 , H01L25/0655 , H01L25/50 , H01L2221/68354 , H01L2221/68359 , H01L2221/68368 , H01L2221/68381 , H01L2224/32225 , H01L2224/75102 , H01L2224/75272 , H01L2224/75745 , H01L2224/75753 , H01L2224/7598 , H01L2224/81005 , H01L2224/81201 , H01L2224/83 , H01L2224/83907 , H01L2224/95001 , H01L2224/95146 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/14 , H01L2924/15788 , H01L2924/3512 , Y10T156/10 , Y10T156/1744 , H01L2924/00014 , H01L2924/00011 , H01L2924/00
摘要： A mounting method of mounting an element on a substrate, includes a first hydrophilization process of hydrophilizing a region on a surface of the substrate where the element is to be joined; a second hydrophilization process of hydrophilizing the surface of the element; a mounting process of mounting the element on a mounting part such that the hydrophilized surface of the element faces upwards; a coating process of coating a liquid on the hydrophilized surface of the element; and an arrangement process of arranging the substrate above the mounting part such that the region on the surface of the substrate where the element is to be joined faces downwards. The method further includes a contact process of bringing the substrate arranged above the mounting part close to the mounting part on which the element is mounted to bring the liquid into contact with the surface of the substrate.
摘要翻译：将元件安装在基板上的安装方法包括使基板的要被接合的基板的表面上的区域亲水化的第一亲水化工序; 使元件的表面亲水化的第二亲水化工序; 将元件安装在安装部分上使得元件的亲水化表面面向上的安装过程; 在所述元件的亲水化表面上涂布液体的涂布方法; 以及将基板布置在安装部分上方以使得要被接合的基板的表面上的区域面向下的布置过程。该方法还包括将安装在安装部分上方的基板靠近安装有元件的安装部分以使液体与基板的表面接触的接触过程。

4. 发明授权

US07701241B2 Circuit for protecting DUT, method for protecting DUT, testing apparatus and testing method 失效
标题翻译：用于保护DUT的电路，用于保护DUT的方法，测试装置和测试方法
公开(公告)号：US07701241B2
公开(公告)日：2010-04-20
申请号：US11689149
申请日：2007-03-21
申请人： Yasunori Kumagai , Dai Shinozaki , Shigekazu Komatsu , Katsuaki Sakamoto
发明人： Yasunori Kumagai , Dai Shinozaki , Shigekazu Komatsu , Katsuaki Sakamoto
IPC分类号： G01R31/26
CPC分类号： G01R31/2889 , G01R1/06766
摘要： A circuit for protecting a DUT is disposed in parallel with a DUT which is supplied with current via wirings and switchable between conducting and non-conducting state. The circuit is switchable between conducting and non-conducing state and switched from non-conducting state to conducting state as the DUT is switched from conducting state to non-conducting state.
摘要翻译：用于保护DUT的电路与被提供有电流经由布线并可在导通状态和非导通状态之间切换的DUT平行设置。该电路可在导通状态和非导通状态之间切换，并且在DUT从导通状态切换到非导通状态时，从非导通状态切换到导通状态。

5. 发明授权

US07586317B2 Inspection apparatus, probe card and inspection method 失效
标题翻译：检验仪器，探针卡及检验方法
公开(公告)号：US07586317B2
公开(公告)日：2009-09-08
申请号：US12174014
申请日：2008-07-16
申请人： Shigekazu Komatsu , Dai Shinozaki , Katsuaki Sakamoto
发明人： Shigekazu Komatsu , Dai Shinozaki , Katsuaki Sakamoto
IPC分类号： G01R1/073
CPC分类号： G01R31/2886 , G01R1/06766 , G01R31/31926
摘要： By allowing an electrical conduction between a probe and an electrode by a fritting phenomenon before inspection, simplification of circuit configuration and shortening of inspection time is achieved. A fritting circuit is formed in a probe card of an inspection apparatus for each probe pair consisting of two probes. A capacitor is connected to each fritting circuit. Each fritting circuit is connected in parallel to a power supply circuit having a charging power supply. Each capacitor is charged at one time by the power supply circuit. The probe pair is brought into contact with an electrode of a wafer, and a high-voltage is applied to the probe pair by a power charged in the capacitor, thereby achieving an electrical connection between each probe and the electrode by a fritting phenomenon. Then, an inspection of electrical characteristics is performed by using an electric inspection signal transmitted to each probe.
摘要翻译：通过在检查之前通过烧结现象允许探针和电极之间的导电，实现电路结构的简化和检查时间的缩短。在由两个探针组成的每个探针对的检查装置的探针卡中形成烧结电路。电容器连接到每个熔接电路。每个熔接电路与具有充电电源的电源电路并联连接。每个电容器由电源电路一次充电。使探针对与晶片的电极接触，并且通过在电容器中充电的电力将高电压施加到探针对，从而通过烧结现象实现每个探针与电极之间的电连接。然后，通过使用发送到每个探针的电检查信号来执行电特性的检查。

6. 发明申请

US20110050269A1 Method for evaluating semiconductor device 有权
标题翻译：半导体器件评估方法
公开(公告)号：US20110050269A1
公开(公告)日：2011-03-03
申请号：US12805273
申请日：2010-07-21
申请人： Mitsuyoshi Miyazono , Shigekazu Komatsu , Dai Shinozaki , Masahiro Kato , Atsushi Yoshida
发明人： Mitsuyoshi Miyazono , Shigekazu Komatsu , Dai Shinozaki , Masahiro Kato , Atsushi Yoshida
IPC分类号： G01R31/26
CPC分类号： H01L22/20 , G01R31/2831 , H01L22/14
摘要： A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved.
摘要翻译：提高半导体模块的产量和生产率。具有导电性的片材固定在其上布置有多个具有表面结构的半导体器件和背面电极的半导体衬底的主表面上。半导体衬底在片材固定到其主表面的状态下在第一支撑台上分成半导体芯片。多个划分的半导体芯片通过片材安装在第二支撑台上，并且多个安装的半导体芯片在第二支撑台上连续进行动态特性测试。所提出的半导体器件评估方法允许抑制在垂直半导体器件的动态特性测试中发生的裂纹的裂缝生长和传播，并且提高半导体模块的产量和生产率。

7. 发明授权

US07301357B2 Inspection method and inspection equipment 失效
标题翻译：检验方法和检验设备
公开(公告)号：US07301357B2
公开(公告)日：2007-11-27
申请号：US10538785
申请日：2003-12-09
申请人： Dai Shinozaki , Shigekazu Komatsu
发明人： Dai Shinozaki , Shigekazu Komatsu
IPC分类号： G01R31/02
CPC分类号： G01R31/2886 , G01R31/2898 , G01R31/3161 , G01R31/31926
摘要： In an inspection method according to the invention, a plurality of drivers 21 incorporated in a tester 20 apply a fritting voltage to respective electrodes P via first probe pins 11A included in pairs of first and second probe pins 11A and 11B and connected to the respective drivers.
摘要翻译：在根据本发明的检查方法中，结合在测试器20中的多个驱动器21通过包括在成对的第一和第二探针11A和11B中的第一探针11A向相应的电极P施加烧结电压，并连接到各自的司机。

8. 发明申请

US20060061374A1 Inspection method and inspection equipment 失效
标题翻译：检验方法和检验设备
公开(公告)号：US20060061374A1
公开(公告)日：2006-03-23
申请号：US10538785
申请日：2003-12-09
申请人： Dai Shinozaki , Shigekazu Komatsu
发明人： Dai Shinozaki , Shigekazu Komatsu
IPC分类号： G01R31/02
CPC分类号： G01R31/2886 , G01R31/2898 , G01R31/3161 , G01R31/31926
摘要： In an inspection method according to the invention, a plurality of drivers 21 incorporated in a tester 20 apply a fritting voltage to respective electrodes P via first probe pins 11A included in pairs of first and second probe pins 11A and 11B and connected to the respective drivers.
摘要翻译：在根据本发明的检查方法中，结合在测试器20中的多个驱动器21通过包括在成对的第一和第二探针11A和11B中的第一探针11A向相应的电极P施加烧结电压，并连接到各自的司机。

9. 发明授权

US08471585B2 Method for evaluating semiconductor device 有权
标题翻译：半导体器件评估方法
公开(公告)号：US08471585B2
公开(公告)日：2013-06-25
申请号：US12805273
申请日：2010-07-21
申请人： Mitsuyoshi Miyazono , Shigekazu Komatsu , Dai Shinozaki , Masahiro Kato , Atsushi Yoshida
发明人： Mitsuyoshi Miyazono , Shigekazu Komatsu , Dai Shinozaki , Masahiro Kato , Atsushi Yoshida
IPC分类号： G01R31/26
CPC分类号： H01L22/20 , G01R31/2831 , H01L22/14
摘要： A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved.
摘要翻译：提高半导体模块的产量和生产率。具有导电性的片材固定在其上布置有多个具有表面结构的半导体器件和背面电极的半导体衬底的主表面上。半导体衬底在片材固定到其主表面的状态下在第一支撑台上分成半导体芯片。多个划分的半导体芯片通过片材安装在第二支撑台上，并且多个安装的半导体芯片在第二支撑台上连续进行动态特性测试。所提出的半导体器件评估方法允许抑制在垂直半导体器件的动态特性测试中发生的裂纹的裂缝生长和传播，并且提高半导体模块的产量和生产率。

10. 发明申请

US20090021272A1 INSPECTION APPARATUS, PROBE CARD AND INSPECTION METHOD 失效
标题翻译：检查装置，检测卡和检查方法
公开(公告)号：US20090021272A1
公开(公告)日：2009-01-22
申请号：US12174014
申请日：2008-07-16
申请人： Shigekazu Komatsu , Dai Shinozaki , Katsuaki Sakamoto
发明人： Shigekazu Komatsu , Dai Shinozaki , Katsuaki Sakamoto
IPC分类号： G01R1/073
CPC分类号： G01R31/2886 , G01R1/06766 , G01R31/31926
摘要： By allowing an electrical conduction between a probe and an electrode by a fritting phenomenon before inspection, simplification of circuit configuration and shortening of inspection time is achieved. A fritting circuit is formed in a probe card of an inspection apparatus for each probe pair consisting of two probes. A capacitor is connected to each fritting circuit. Each fritting circuit is connected in parallel to a power supply circuit having a charging power supply. Each capacitor is charged at one time by the power supply circuit. The probe pair is brought into contact with an electrode of a wafer, and a high-voltage is applied to the probe pair by a power charged in the capacitor, thereby achieving an electrical connection between each probe and the electrode by a fritting phenomenon. Then, an inspection of electrical characteristics is performed by using an electric inspection signal transmitted to each probe.
摘要翻译：通过在检查之前通过烧结现象允许探针和电极之间的导电，实现电路结构的简化和检查时间的缩短。在由两个探针组成的每个探针对的检查装置的探针卡中形成烧结电路。电容器连接到每个熔接电路。每个熔接电路与具有充电电源的电源电路并联连接。每个电容器由电源电路一次充电。使探针对与晶片的电极接触，并且通过在电容器中充电的电力将高电压施加到探针对，从而通过烧结现象实现每个探针与电极之间的电连接。然后，通过使用发送到每个探针的电检查信号来执行电特性的检查。

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