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    • 2. 发明授权
      US4868420A Flip-flop circuit 失效
    • Flip-flop circuit
    • 触发电路
    • US4868420A
    • 1989-09-19
    • US273729
    • 1988-11-18
    • Hiroyuki Itoh , Masayoshi Yagyu , Toshio Yamada , Masaru Osanai , Akira Masaki , Mitsuo Usami , Tohru Kobayashi , Masato Hamamoto
    • Hiroyuki Itoh , Masayoshi Yagyu , Toshio Yamada , Masaru Osanai , Akira Masaki , Mitsuo Usami , Tohru Kobayashi , Masato Hamamoto
    • H03K3/037 , H03K3/2885
    • H03K3/2885 , H03K3/0375
    • An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to .alpha. rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first logic circuit which holds data and produces a first logic signal and a second logic circuit which produces a second logic signal. A logic gate receives the first and second logic signals that are produced from the first and second logic circuits and which have the same logic level. The output of the logic gate is input to the first logic circuit through a feedback loop which is provided between the output and the input of the first logic circuit and which includes the logic gate. According to the circuit construction of the present invention, a flip-flop circuit can be accomplished which is resistant to the radioactive rays such as .alpha. rays and does not cause soft errors.
    • 提供一种改进的触发器电路，其防止由包含在半导体封装材料中的痕量放射性材料发射的α射线等引起的软误差的发生。 触发器电路具有保持数据并产生第一逻辑信号的第一逻辑电路和产生第二逻辑信号的第二逻辑电路。 逻辑门接收从第一和第二逻辑电路产生并具有相同逻辑电平的第一和第二逻辑信号。 逻辑门的输出通过反馈回路输入到第一逻辑电路，反馈回路设置在第一逻辑电路的输出端和输入端之间，并包括逻辑门。 根据本发明的电路结构，可以实现对诸如α射线的放射线的耐受性并且不引起软错误的触发器电路。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US5394490A Semiconductor device having an optical waveguide interposed in the space between electrode members 失效
    • Semiconductor device having an optical waveguide interposed in the space between electrode members
    • 具有插入在电极构件之间的空间的光波导的半导体装置
    • US5394490A
    • 1995-02-28
    • US104582
    • 1993-08-11
    • Takeshi Kato , Yuuji Fujita , Kenichi Mizuishi , Atumi Kawata , Hiroyuki Itoh
    • Takeshi Kato , Yuuji Fujita , Kenichi Mizuishi , Atumi Kawata , Hiroyuki Itoh
    • G02B6/12 , G02B6/13 , G02B6/30 , G02B6/42 , G02B6/43 , G06F1/10 , H05K1/00
    • G02B6/43 , G02B6/13 , G02B6/30 , G02B6/42 , G06F1/105 , G02B2006/12104 , G02B6/4232 , H01L2224/16237 , H01L2224/73253 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/15312 , H01L2924/16195 , H01L2924/3011 , H01L2924/3025
    • A clock signal supply system is disclosed for a semiconductor device with a semiconductor chip and a wiring substrate connected in flip-chip fashion and an optical waveguide interposed in the space between electrode members, in which the mutual arrangement of the electrical interconnection and the optical waveguide interconnection on the wiring substrate is not affected and can be used separately from each other for different applications, thereby improving the throughput of the interconnections as a whole. In order to distribute a very fast clock signal beyond a 1 GHz in particular without any phase deviation in the clock signal supply system, a clock distributor includes a clock oscillator, a phase adjuster for adjusting the phase at each destination of the clock signal, an optical interconnection for supplying the clock signal to the phase adjuster, a reference signal generator for generating a phase reference signal from the clock signal, and an electrical interconnection for supplying the reference signal to the phase adjuster. The clock signal is supplied by an optical interconnection having a broad frequency bandwidth, and the phase reference signal by an electrical interconnection by which the skew is controlled easily. A clock signal adjusted to high phase accuracy can thus be distributed to following destinations by the phase adjuster.
    • 公开了一种半导体器件的时钟信号供给系统，半导体器件具有以倒装芯片方式连接的半导体芯片和布线基板，以及插入在电极部件之间的空间中的光波导，其中电互连和光波导 布线基板上的互连不受影响，并且可以彼此分开地用于不同的应用，从而提高互连的整体的吞吐量。 为了在非常快的时钟信号中分配非常快的时钟信号，特别是在时钟信号供给系统中没有任何相位偏差，时钟分配器包括时钟振荡器，用于调整时钟信号的每个目的地的相位的相位调节器， 用于向相位调节器提供时钟信号的光互连，用于从时钟信号产生相位参考信号的参考信号发生器和用于将参考信号提供给相位调节器的电互连。 时钟信号由具有宽频带宽的光互连提供，并且相位参考信号由通过电互连的相位参考信号提供，通过该互连可以容易地控制偏斜。 因此，调整到高相位精度的时钟信号可以由相位调节器分配到后续目的地。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5184027A Clock signal supply system 失效
    • Clock signal supply system
    • 时钟信号供电系统
    • US5184027A
    • 1993-02-02
    • US688696
    • 1991-04-22
    • Noboru Masuda , Ryotaro Kamikawai , Masayoshi Yagyu , Masakazu Yamamoto , Hiroyuki Itoh , Tatsuya Saito
    • Noboru Masuda , Ryotaro Kamikawai , Masayoshi Yagyu , Masakazu Yamamoto , Hiroyuki Itoh , Tatsuya Saito
    • C04B35/45 , G06F1/10 , H01L39/12 , H01L39/24
    • C04B35/4504 , G06F1/10 , H01L39/126 , H01L39/2419
    • A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship with respect to the clock signals produced by the oscillator. At each location where the clock signal is to be received, an adjusting circuit is provided to adjust the phase of the received clock signals. Such an adjusting circuit may include a variable delay circuit which receives the clock signal and produces an output which is constituted by the clock signal having a varied delay, to the remainder of the attached circuits. Further, the output of the variable delay is fed back to a phase difference detection circuit. The reference signal is second input to the phase difference detection circuit. This phase difference detection circuit compares the difference of the reference signal and the output of the variable delay circuit and produces the control signal to the variable delay circuit which will further adjust the phase of the clock signal that is received. This adjustment is carried out at each of the locations where the clock signal is to be received, thereby providing automatic adjustment of the phase of the clock signals.
    • 时钟信号供应系统提供时钟信号的自动精确相位调整。 该系统包括产生时钟信号的振荡器和产生相对于由振荡器产生的时钟信号具有预定关系的参考信号的参考发生器。 在要接收时钟信号的每个位置，提供调整电路以调整所接收的时钟信号的相位。 这种调整电路可以包括可变延迟电路，其接收时钟信号并且产生由具有变化的延迟的时钟信号构成的输出到连接电路的其余部分。 此外，可变延迟的输出被反馈到相位差检测电路。 参考信号是相位差检测电路的第二输入。 该相位差检测电路比较参考信号和可变延迟电路的输出的差异，并将该控制信号产生到可变延迟电路，该可变延迟电路将进一步调节所接收的时钟信号的相位。 该调整是在要接收时钟信号的每个位置处执行的，从而提供对时钟信号的相位的自动调整。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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