专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080152840A1 APPARATUS FOR INTEGRATED GAS AND RADIATION DELIVERY 有权
标题翻译：集成气体和辐射输送装置
公开(公告)号：US20080152840A1
公开(公告)日：2008-06-26
申请号：US11615633
申请日：2006-12-22
申请人： MARTIN JOHN RIPLEY , Sean M. Seutter
发明人： MARTIN JOHN RIPLEY , Sean M. Seutter
IPC分类号： C23C16/00
CPC分类号： C23C16/45565
摘要： An apparatus for photo-assisted or photo-induced processes is disclosed, comprising a process chamber having an integrated gas and radiation distribution plate. In one embodiment, the plate has one set of apertures for distributing one or more process gases, and another set of apertures for distributing radiation to a process region in the chamber.
摘要翻译：公开了一种用于光辅助或光引发工艺的装置，包括具有集成的气体和辐射分布板的处理室。在一个实施例中，板具有用于分配一个或多个处理气体的一组孔，以及用于将辐射分配到室中的处理区域的另一组孔。

2. 发明授权

US07922863B2 Apparatus for integrated gas and radiation delivery 有权
标题翻译：用于集成气体和辐射输送的装置
公开(公告)号：US07922863B2
公开(公告)日：2011-04-12
申请号：US11615633
申请日：2006-12-22
申请人： Martin John Ripley , Sean M. Seutter
发明人： Martin John Ripley , Sean M. Seutter
IPC分类号： H01L21/306 , C23F1/00 , C23C16/00
CPC分类号： C23C16/45565
摘要： An apparatus for photo-assisted or photo-induced processes is disclosed, comprising a process chamber having an integrated gas and radiation distribution plate. In one embodiment, the plate has one set of apertures for distributing one or more process gases, and another set of apertures for distributing radiation to a process region in the chamber.
摘要翻译：公开了一种用于光辅助或光引发工艺的装置，包括具有集成的气体和辐射分布板的处理室。在一个实施例中，板具有用于分配一个或多个处理气体的一组孔，以及用于将辐射分配到室中的处理区域的另一组孔。

3. 发明授权

US09892941B2 Multi-zone resistive heater 有权
公开(公告)号：US09892941B2
公开(公告)日：2018-02-13
申请号：US12485160
申请日：2009-06-16
申请人： Anqing Cui , Binh Tran , Alexander Tam , Jacob W. Smith , R. Suryanarayanan Iyer , Joseph Yudovsky , Sean M. Seutter
发明人： Anqing Cui , Binh Tran , Alexander Tam , Jacob W. Smith , R. Suryanarayanan Iyer , Joseph Yudovsky , Sean M. Seutter
IPC分类号： H05B3/68 , H01L21/67
CPC分类号： H01L21/67103 , H01L21/67248 , H05B3/68
摘要： Apparatus, reactors, and methods for heating substrates are disclosed. The apparatus comprises a stage comprising a body and a surface having an area to support a substrate, a shaft coupled to the stage, a first heating element disposed within a central region of the body of the stage, and at least second and third heating elements disposed within the body of the stage, the at least second and third heating elements each partially surrounding the first heating element and wherein the at least second and third heating elements are circumferentially adjacent to each other.

4. 发明授权

US09502521B2 Multi-layer charge trap silicon nitride/oxynitride layer engineering with interface region control 有权
标题翻译：多层电荷阱氮化硅/氮氧化物层工程与界面区域控制
公开(公告)号：US09502521B2
公开(公告)日：2016-11-22
申请号：US13189225
申请日：2011-07-22
申请人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
发明人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
IPC分类号： H01L21/28 , H01L29/51
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/518
摘要： A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.
摘要翻译：一种非易失性存储器半导体器件，包括在沟道上方具有沟道和栅极堆叠的半导体衬底。栅极堆叠包括与沟道相邻的隧道层，隧道层上方的电荷俘获层，电荷俘获层上方的电荷阻挡层，电荷阻挡层上方的控制栅极以及电荷俘获之间有意并入的界面区域层和电荷阻挡层。电荷捕获层包括包含硅和氮的化合物，电荷阻挡层含有电荷阻挡组分的氧化物，并且界面区域包括包含硅，氮和电荷阻挡组分的化合物。隧道层可以包括多达三个隧道子层，电荷捕获层可以包括两个陷阱子层，并且电荷阻挡层可以包括多达五个阻塞子层。可以采用各种栅堆叠形成技术。

5. 发明授权

US08946547B2 Backplane reinforcement and interconnects for solar cells 有权
标题翻译：太阳能电池背板加固和互连
公开(公告)号：US08946547B2
公开(公告)日：2015-02-03
申请号：US13204626
申请日：2011-08-05
申请人： Mehrdad M. Moslehi , David Xuan-Qi Wang , Karl-Josef Kramer , Sean M. Seutter , Sam Tone Tor , Anthony Calcaterra
发明人： Mehrdad M. Moslehi , David Xuan-Qi Wang , Karl-Josef Kramer , Sean M. Seutter , Sam Tone Tor , Anthony Calcaterra
IPC分类号： H01L31/00 , H01L31/05 , H01L31/0224
CPC分类号： H01L31/022458 , H01L31/02008 , H01L31/02013 , H01L31/022441 , H01L31/028 , H01L31/0516 , H01L31/0682 , H01L31/1804 , H01L31/1892 , Y02E10/50
摘要： Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, forming electrically conductive emitter plugs and base plugs on the interdigitated pattern, and attaching a backplane having a second interdigitated pattern of base electrodes and emitter electrodes at the conductive emitter and base plugs to form electrical interconnects.
摘要翻译：描述了提供太阳能电池基板加强和电互连的背接触太阳能电池的背板的制造方法和结构。该方法包括在半导体衬底的背面上沉积基底电极和发射电极的交错图案，在交叉图案上形成导电发射器插头和基座插头，并且附接具有第二互补图案的基极和发射极的背板在导电发射器和基座插头上形成电互连。

6. 发明授权

US08114789B2 Formation of a tantalum-nitride layer 失效
标题翻译：形成氮化钽层
公开(公告)号：US08114789B2
公开(公告)日：2012-02-14
申请号：US12846253
申请日：2010-07-29
申请人： Sean M. Seutter , Michael X. Yang , Ming Xi
发明人： Sean M. Seutter , Michael X. Yang , Ming Xi
IPC分类号： H01L21/469
CPC分类号： C23C16/45553 , C23C16/34 , C23C16/4554 , C23C16/56 , H01L21/28562 , H01L21/28568 , H01L21/76844 , H01L21/76862
摘要： A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.
摘要翻译：公开了一种在衬底上形成材料的方法。在一个实施例中，该方法包括在设置在等离子体处理室中的衬底上形成氮化钽层，通过将衬底顺序地暴露于钽前体和氮前体，然后通过暴露衬底来降低氮化钽层的氮浓度等离子体退火工艺。随后在氮化钽层上沉积含金属的层。

7. 发明申请

US20110101442A1 Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control 审中-公开
标题翻译：多层电荷陷阱氮化硅/氮氧化物层工程与界面区域控制
公开(公告)号：US20110101442A1
公开(公告)日：2011-05-05
申请号：US12610457
申请日：2009-11-02
申请人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
发明人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/513 , H01L29/40117 , H01L29/518
摘要： A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.
摘要翻译：一种非易失性存储器半导体器件，包括在沟道上方具有沟道和栅极堆叠的半导体衬底。栅极堆叠包括与沟道相邻的隧道层，隧道层上方的电荷俘获层，电荷俘获层上方的电荷阻挡层，电荷阻挡层上方的控制栅极以及电荷俘获之间有意并入的界面区域层和电荷阻挡层。电荷捕获层包括包含硅和氮的化合物，电荷阻挡层含有电荷阻挡组分的氧化物，并且界面区域包括包含硅，氮和电荷阻挡组分的化合物。隧道层可以包括多达三个隧道子层，电荷捕获层可以包括两个陷阱子层，并且电荷阻挡层可以包括多达五个阻塞子层。可以采用各种栅堆叠形成技术。

8. 发明申请

US20110281429A1 Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control 有权
公开(公告)号：US20110281429A1
公开(公告)日：2011-11-17
申请号：US13189225
申请日：2011-07-22
申请人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
发明人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
IPC分类号： H01L21/283
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/518
摘要： A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.

9. 发明授权

US07781326B2 Formation of a tantalum-nitride layer 有权
标题翻译：形成氮化钽层
公开(公告)号：US07781326B2
公开(公告)日：2010-08-24
申请号：US11240189
申请日：2005-09-30
申请人： Sean M. Seutter , Michael X. Yang , Ming Xi
发明人： Sean M. Seutter , Michael X. Yang , Ming Xi
IPC分类号： H01L21/4763
CPC分类号： C23C16/45553 , C23C16/34 , C23C16/4554 , C23C16/56 , H01L21/28562 , H01L21/28568 , H01L21/76844 , H01L21/76862
摘要： A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.
摘要翻译：公开了一种在衬底上形成材料的方法。在一个实施例中，该方法包括在设置在等离子体处理室中的衬底上形成氮化钽层，通过将衬底顺序地暴露于钽前体和氮前体，然后通过暴露衬底来降低氮化钽层的氮浓度等离子体退火工艺。随后在氮化钽层上沉积含金属的层。

10. 发明授权

US07094680B2 Formation of a tantalum-nitride layer 有权
标题翻译：形成氮化钽层
公开(公告)号：US07094680B2
公开(公告)日：2006-08-22
申请号：US11088072
申请日：2005-03-23
申请人： Sean M. Seutter , Michael X. Yang , Ming Xi
发明人： Sean M. Seutter , Michael X. Yang , Ming Xi
IPC分类号： H01L21/4763
CPC分类号： C23C16/45553 , C23C16/34 , C23C16/4554 , C23C16/56 , H01L21/28562 , H01L21/28568 , H01L21/76844 , H01L21/76862
摘要： A method of forming a tantalum nitride layer for integrated circuit fabrication is disclosed. In one embodiment, the method includes forming a tantalum nitride layer by chemisorbing a tantalum precursor and a nitrogen precursor on a substrate disposed in a process chamber. A nitrogen concentration of the tantalum nitride layer is reduced by exposing the substrate to a plasma annealing process. A metal-containing layer is then deposited on the tantalum nitride layer by a deposition process.
摘要翻译：公开了一种形成用于集成电路制造的氮化钽层的方法。在一个实施例中，该方法包括通过在设置在处理室中的衬底上化学吸附钽前体和氮前体来形成氮化钽层。氮化钽层的氮浓度通过将衬底暴露于等离子体退火工艺而降低。然后通过沉积工艺将含金属的层沉积在氮化钽层上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式