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1. 发明申请

US20110281429A1 Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control 有权
公开(公告)号：US20110281429A1
公开(公告)日：2011-11-17
申请号：US13189225
申请日：2011-07-22
申请人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
发明人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
IPC分类号： H01L21/283
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/518
摘要： A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.

2. 发明授权

US09502521B2 Multi-layer charge trap silicon nitride/oxynitride layer engineering with interface region control 有权
标题翻译：多层电荷阱氮化硅/氮氧化物层工程与界面区域控制
公开(公告)号：US09502521B2
公开(公告)日：2016-11-22
申请号：US13189225
申请日：2011-07-22
申请人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
发明人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
IPC分类号： H01L21/28 , H01L29/51
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/518
摘要： A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.
摘要翻译：一种非易失性存储器半导体器件，包括在沟道上方具有沟道和栅极堆叠的半导体衬底。栅极堆叠包括与沟道相邻的隧道层，隧道层上方的电荷俘获层，电荷俘获层上方的电荷阻挡层，电荷阻挡层上方的控制栅极以及电荷俘获之间有意并入的界面区域层和电荷阻挡层。电荷捕获层包括包含硅和氮的化合物，电荷阻挡层含有电荷阻挡组分的氧化物，并且界面区域包括包含硅，氮和电荷阻挡组分的化合物。隧道层可以包括多达三个隧道子层，电荷捕获层可以包括两个陷阱子层，并且电荷阻挡层可以包括多达五个阻塞子层。可以采用各种栅堆叠形成技术。

3. 发明申请

US20110101442A1 Multi-Layer Charge Trap Silicon Nitride/Oxynitride Layer Engineering with Interface Region Control 审中-公开
标题翻译：多层电荷陷阱氮化硅/氮氧化物层工程与界面区域控制
公开(公告)号：US20110101442A1
公开(公告)日：2011-05-05
申请号：US12610457
申请日：2009-11-02
申请人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
发明人： Udayan Ganguly , Christopher S. Olsen , Sean M. Seutter , Lucien Date
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/513 , H01L29/40117 , H01L29/518
摘要： A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.
摘要翻译：一种非易失性存储器半导体器件，包括在沟道上方具有沟道和栅极堆叠的半导体衬底。栅极堆叠包括与沟道相邻的隧道层，隧道层上方的电荷俘获层，电荷俘获层上方的电荷阻挡层，电荷阻挡层上方的控制栅极以及电荷俘获之间有意并入的界面区域层和电荷阻挡层。电荷捕获层包括包含硅和氮的化合物，电荷阻挡层含有电荷阻挡组分的氧化物，并且界面区域包括包含硅，氮和电荷阻挡组分的化合物。隧道层可以包括多达三个隧道子层，电荷捕获层可以包括两个陷阱子层，并且电荷阻挡层可以包括多达五个阻塞子层。可以采用各种栅堆叠形成技术。

4. 发明申请

US20110061812A1 Apparatus and Methods for Cyclical Oxidation and Etching 审中-公开
公开(公告)号：US20110061812A1
公开(公告)日：2011-03-17
申请号：US12720926
申请日：2010-03-10
申请人： Udayan Ganguly , Yoshitaka Yokota , Christopher S. Olsen , Matthew D. Scotney-Castle , Vicky Nguyen , Swaminathan Srinivasan , Wei Liu , Johanes F. Swenberg , Jose A. Marin , Aijit Balakrishna , Jacob Newman , Stephen C. Hickerson
发明人： Udayan Ganguly , Yoshitaka Yokota , Christopher S. Olsen , Matthew D. Scotney-Castle , Vicky Nguyen , Swaminathan Srinivasan , Wei Liu , Johanes F. Swenberg , Jose A. Marin , Aijit Balakrishna , Jacob Newman , Stephen C. Hickerson
IPC分类号： H01L21/465
CPC分类号： H01L21/0223 , H01L21/67109 , H01L21/67115 , H01L21/67167 , H01L21/6719 , H01L21/67207 , H01L21/68785 , H01L21/76232 , H01L27/11521
摘要： Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

5. 发明申请

US20110061810A1 Apparatus and Methods for Cyclical Oxidation and Etching 审中-公开
标题翻译：循环氧化和蚀刻的装置和方法
公开(公告)号：US20110061810A1
公开(公告)日：2011-03-17
申请号：US12720957
申请日：2010-03-10
申请人： Udayan Ganguly , Joseph M. Ranish , Aaron M. Hunter , Jing Tang , Christopher S. Olsen , Matthew D. Scotney-Castle , Vicky Nguyen , Swaminathan Srinivasan , Johanes F. Swenberg , Anchuan Wang , Nitin K. Ingle , Manish Hemkar , Jose A. Marin
发明人： Udayan Ganguly , Joseph M. Ranish , Aaron M. Hunter , Jing Tang , Christopher S. Olsen , Matthew D. Scotney-Castle , Vicky Nguyen , Swaminathan Srinivasan , Johanes F. Swenberg , Anchuan Wang , Nitin K. Ingle , Manish Hemkar , Jose A. Marin
IPC分类号： H01L21/3065
CPC分类号： H01L21/67115 , H01L21/0223 , H01L21/67109 , H01L21/67167 , H01L21/6719 , H01L21/67207 , H01L21/68785 , H01L21/76232 , H01L27/11521
摘要： Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.
摘要翻译：本文描述了用于制造适用于窄间距应用的半导体器件的装置和方法及其制造方法。公开了通过氧化材料层的表面以形成氧化物层来形成和/或形成材料层的各种单室; 通过蚀刻工艺去除至少一些氧化物层; 并周期性地重复氧化和去除工艺，直到材料层形成所需的形状。在一些实施例中，材料层可以是半导体器件的浮置栅极。

6. 发明授权

US07972933B2 Method of selective nitridation 有权
标题翻译：选择性氮化方法
公开(公告)号：US07972933B2
公开(公告)日：2011-07-05
申请号：US12748523
申请日：2010-03-29
申请人： Christopher S. Olsen , Johanes Swenberg , Udayan Ganguly , Theresa Kramer Guarini , Yonah Cho
发明人： Christopher S. Olsen , Johanes Swenberg , Udayan Ganguly , Theresa Kramer Guarini , Yonah Cho
IPC分类号： H01L21/76
CPC分类号： H01L21/3144 , H01L21/02247 , H01L21/02326 , H01L21/02332 , H01L21/0234 , H01L21/3211 , H01L27/11521 , Y10S438/911
摘要： Methods of forming semiconductor devices are provided herein. In some embodiments, a method of forming a semiconductor device may include providing a substrate having an oxide surface and a silicon surface; forming a nitrogen-containing layer on exposed portions of both the oxide and silicon surfaces; and oxidizing the nitrogen-containing layer to selectively remove the nitrogen-containing layer from atop the oxide surface. In some embodiments, an oxide layer is formed atop a remaining portion of the nitrogen-containing layer formed on the silicon feature. In some embodiments, the oxide surface is an exposed surface of a shallow trench isolate region (STI) disposed adjacent to one or more floating gates of a semiconductor device. In some embodiments, the silicon surface is an exposed surface of a silicon or polysilicon floating gate of a semiconductor device.
摘要翻译：本文提供了形成半导体器件的方法。在一些实施例中，形成半导体器件的方法可以包括提供具有氧化物表面和硅表面的衬底; 在氧化物和硅表面的暴露部分上形成含氮层; 并氧化含氮层以从氧化物表面顶部选择性地除去含氮层。在一些实施例中，在形成于硅特征上的含氮层的剩余部分的顶部形成氧化物层。在一些实施例中，氧化物表面是与半导体器件的一个或多个浮动栅极相邻设置的浅沟槽隔离区域（STI）的暴露表面。在一些实施例中，硅表面是半导体器件的硅或多晶硅浮置栅极的暴露表面。

7. 发明申请

US20110065276A1 Apparatus and Methods for Cyclical Oxidation and Etching 审中-公开
公开(公告)号：US20110065276A1
公开(公告)日：2011-03-17
申请号：US12720942
申请日：2010-03-10
申请人： Udayan Ganguly , Joseph M. Ranish , Aaron M. Hunter , Jing Tang , Christopher S. Olsen , Matthew D. Scotney-Castle , Vicky Nguyen , Swaminathan Srinivasan , Wei Liu , Johanes F. Swenberg , Shiyu Sun
发明人： Udayan Ganguly , Joseph M. Ranish , Aaron M. Hunter , Jing Tang , Christopher S. Olsen , Matthew D. Scotney-Castle , Vicky Nguyen , Swaminathan Srinivasan , Wei Liu , Johanes F. Swenberg , Shiyu Sun
IPC分类号： H01L21/311 , H01L21/3065
CPC分类号： H01L21/76232 , H01L21/0223 , H01L21/67109 , H01L21/67115 , H01L21/67167 , H01L21/6719 , H01L21/67207 , H01L21/68785 , H01L27/11521
摘要： Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

8. 发明授权

US08163343B2 Method of forming an aluminum oxide layer 失效
标题翻译：形成氧化铝层的方法
公开(公告)号：US08163343B2
公开(公告)日：2012-04-24
申请号：US12203647
申请日：2008-09-03
申请人： Shreyas S. Kher , Christopher S. Olsen , Lucien Date
发明人： Shreyas S. Kher , Christopher S. Olsen , Lucien Date
IPC分类号： C23C16/40
CPC分类号： C23C16/403 , C23C16/0272 , H01L21/02178 , H01L21/02271 , H01L21/31616
摘要： Methods of forming aluminum oxide layers on substrates are disclosed. In some embodiments, the method includes depositing an aluminum oxide seed layer on the substrate using a first process having a first deposition rate. The method further includes depositing a bulk aluminum oxide layer atop the seed layer using a metalorganic chemical vapor deposition (MOCVD) process having a second deposition rate greater than the first deposition rate.
摘要翻译：公开了在基底上形成氧化铝层的方法。在一些实施例中，该方法包括使用具有第一沉积速率的第一工艺在衬底上沉积氧化铝种子层。该方法还包括使用具有大于第一沉积速率的第二沉积速率的金属有机化学气相沉积（MOCVD）工艺沉积种子层顶部的体积氧化铝层。

9. 发明申请

US20130137249A1 REMOTE RADICAL HYDRIDE DOPANT INCORPORATION FOR DELTA DOPING IN SILICON 有权
标题翻译：用于紫外线去离子的远程放射性掺杂剂
公开(公告)号：US20130137249A1
公开(公告)日：2013-05-30
申请号：US13676703
申请日：2012-11-14
申请人： Christopher S. Olsen , Johanes S. Swenberg
发明人： Christopher S. Olsen , Johanes S. Swenberg
IPC分类号： H01L21/263
CPC分类号： H01L21/263 , H01J37/32357 , H01L21/2236
摘要： The present invention generally relates to methods of forming substrates using remote radical hydride doping. The methods generally include remotely activating a gas and introducing activated radicals of the gas into a chamber. The activated radicals may be activated hydride radicals of a gas such as diborane (B2H6), phosphine (PH3), or arsine (AsH3) which are utilized to incorporate an element such as boron, phosphorus, or arsenic into a substrate having a surface temperature between about 400 degrees Celsius and about 1000 degrees Celsius. Alternatively, the activated radicals may be activated radicals of an inert gas. The activated radicals of the inert gas are introduced into a chamber having a dopant-containing gas, such as diborane, phosphine, or arsine, therein. The activated radicals of the inert gas activate the dopant-gas and incorporate dopants into a heated substrate located within the chamber.
摘要翻译：本发明一般涉及使用远程自由基氢化物掺杂形成衬底的方法。所述方法通常包括远程激活气体并将气体的活化自由基引入室中。活化的基团可以是诸如乙硼烷（B 2 H 6），膦（PH 3）或胂（AsH 3）的气体的活化氢化物基团，其用于将诸如硼，磷或砷的元素掺入具有表面温度介于约400摄氏度和约1000摄氏度之间。或者，活化的自由基可以是惰性气体的活化基团。将惰性气体的活化基团引入到其中具有含掺杂剂气体的室中，例如乙硼烷，膦或胂。惰性气体的活化自由基激活掺杂剂气体，并将掺杂剂掺入到位于室内的加热衬底中。

10. 发明授权

US08168462B2 Passivation process for solar cell fabrication 失效
标题翻译：太阳能电池制造的钝化过程
公开(公告)号：US08168462B2
公开(公告)日：2012-05-01
申请号：US12479139
申请日：2009-06-05
申请人： Peter Borden , Michael P. Stewart , Li Xu , Hemant P. Mungekar , Christopher S. Olsen
发明人： Peter Borden , Michael P. Stewart , Li Xu , Hemant P. Mungekar , Christopher S. Olsen
IPC分类号： H01L21/00 , H01L31/0216
CPC分类号： H01L31/1868 , H01L31/022425 , H01L31/072 , Y02E10/50 , Y02P70/521
摘要： Embodiments of the invention contemplate the formation of a high efficiency solar cell using a novel plasma oxidation process to form a passivation film stack on a surface of a solar cell substrate. In one embodiment, the methods include providing a substrate having a first type of doping atom on a back surface of the substrate and a second type of doping atom on a front surface of the substrate, plasma oxidizing the back surface of the substrate to form an oxidation layer thereon, and forming a silicon nitride layer on the oxidation layer.
摘要翻译：本发明的实施例考虑使用新颖的等离子体氧化工艺形成高效太阳能电池，以在太阳能电池基板的表面上形成钝化膜堆叠。在一个实施方案中，所述方法包括提供在衬底的背面上具有第一类型的掺杂原子的衬底和在衬底的前表面上的第二类型的掺杂原子，等离子体氧化衬底的背表面以形成氧化层，并在氧化层上形成氮化硅层。

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