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1. 发明申请

US20050086575A1 Generalized parity stripe data storage array 失效
标题翻译：广义奇偶条纹数据存储阵列
公开(公告)号：US20050086575A1
公开(公告)日：2005-04-21
申请号：US10689814
申请日：2003-10-20
申请人： Martin Hassner , Steven Hetzler , Tetsuya Tamura , Barry Trager , Shmuel Winograd
发明人： Martin Hassner , Steven Hetzler , Tetsuya Tamura , Barry Trager , Shmuel Winograd
IPC分类号： G11C29/00 , H03M13/29
CPC分类号： H03M13/2909 , G06F11/1076 , H03M13/134 , H03M13/2906
摘要： The Hamming distance of an array of storage devices is increased by generating a parity check matrix based on column equations that are formed using an orthogonal parity code and includes a higher-order multiplier that changes each column. The higher order multiplier is selected to generate a finite basic field of a predetermined number of elements. The array has M rows and N columns, such that M is greater than or equal to three and N is greater than or equal to three. Row 1 through row M-2 of the array each have n-p data storage devices and p parity storage devices. Row M-1 of the array has n-(p+1) data storage devices and (p+1) parity storage devices. Lastly, row M of the array has N parity storage devices.
摘要翻译：存储装置阵列的汉明距离通过基于使用正交奇偶校验码形成的列方程生成奇偶校验矩阵而增加，并且包括改变每列的高阶乘法器。选择较高阶乘数以产生预定数量的元素的有限基本场。阵列具有M行和N列，使得M大于或等于3，N大于或等于3。阵列的行1至行M-2各自具有n-p个数据存储设备和p个奇偶校验存储设备。阵列的行M-1具有n（p + 1）数据存储设备和（p + 1）奇偶校验存储设备。最后，数组的行M具有N个奇偶校验存储设备。

2. 发明授权

US5428628A Modular implementation for a parallelized key equation solver for linear algebraic codes 失效
标题翻译：用于线性代数代码的并行化关键方程求解器的模块化实现
公开(公告)号：US5428628A
公开(公告)日：1995-06-27
申请号：US127465
申请日：1993-09-27
申请人： Martin Hassner , Uwe Schwiegelshohn , Shmuel Winograd
发明人： Martin Hassner , Uwe Schwiegelshohn , Shmuel Winograd
IPC分类号： G06F11/10 , H03M13/00 , H03M13/15
CPC分类号： H03M13/151
摘要： Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. Circuitry implements two computation sequences. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two sequences being required to decode t symbols in error. These sequences are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in the other sequence being paired with a multiplication operation in the next iteration of the one sequence. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed. Two consecutive executions of the other sequence are prevented.
摘要翻译：用于实现用于解码线性代数码的解码的关键方程的并行算法的装置和方法。电路实现两个计算序列。其中一个执行三个乘法运算，另一个执行五个乘法运算，需要这两个序列的2t次迭代来解码错误的t个符号。这些序列被耦合，使得在每个连续的2t迭代期间，四个乘法运算被成对同时执行，另一个序列中的第五次乘法运算与在一个序列的下一次迭代中的乘法运算配对。在一对配对乘法运算中，执行逆表查找操作，而在另一乘法运算期间，执行加法运算。防止其他顺序的两个连续执行。

3. 发明申请

US20080016413A1 RAID 3 + 3 有权
公开(公告)号：US20080016413A1
公开(公告)日：2008-01-17
申请号：US11747887
申请日：2007-05-11
申请人： Steven Hetzler , Daniel Smith , Shmuel Winograd
发明人： Steven Hetzler , Daniel Smith , Shmuel Winograd
IPC分类号： G06F11/00
CPC分类号： G06F11/1076 , G06F2211/1057 , G06F2211/1059 , G06F2211/1064
摘要： A data storage subsystem that includes three data storage units, three check storage units, and an array controller coupled to the three data and three check storage units can tolerate failure of any three data and check storage units failures can be occur before data stored on the data storage subsystem is lost. Information is stored on the data storage subsystem as a symmetric Maximum Distance Separation code, such as a Winograd code, a Reed Solomon code, an EVENODD code or a derivative of an EVENODD code. The array controller determines the contents of the check storage units so that any three erasures of the data storage units and the check storage units can be corrected by the array controller. The array controller updates a block of data contained in any one of the data storage units and the check storage units using only six IO operations.
摘要翻译：包含三个数据存储单元，三个检查存储单元和耦合到三个数据的阵列控制器和三个检查存储单元的数据存储子系统可以容忍任何三个数据的故障，并且检查存储单元可能在存储在数据存储子系统丢失。信息作为对称的最大距离分离码存储在数据存储子系统上，例如Winograd码，里德所罗门码，EVENODD码或EVENODD码的导数。阵列控制器确定检查存储单元的内容，使得数据存储单元和检查存储单元的任何三个擦除可以由阵列控制器校正。阵列控制器仅使用六个IO操作来更新包含在数据存储单元和检查存储单元中的任何一个中的数据块。

4. 发明申请

US20050015700A1 Raid 3 + 3 有权
标题翻译：突击3 + 3
公开(公告)号：US20050015700A1
公开(公告)日：2005-01-20
申请号：US10619648
申请日：2003-07-14
申请人： Steven Hetzler , Daniel Smith , Shmuel Winograd
发明人： Steven Hetzler , Daniel Smith , Shmuel Winograd
IPC分类号： G06F3/06 , G06F11/10 , G11C29/00
CPC分类号： G06F11/1076 , G06F2211/1057 , G06F2211/1059 , G06F2211/1064
摘要： A data storage subsystem that includes three data storage units, three check storage units, and an array controller coupled to the three data and three check storage units can tolerate failure of any three data and check storage units failures can be occur before data stored on the data storage subsystem is lost. Information is stored on the data storage subsystem as a symmetric Maximum Distance Separation code, such as a Winograd code, a Reed Solomon code, an EVENODD code or a derivative of an EVENODD code. The array controller determines the contents of the check storage units so that any three erasures of the data storage units and the check storage units can be corrected by the array controller. The array controller updates a block of data contained in any one of the data storage units and the check storage units using only six IO operations.
摘要翻译：包含三个数据存储单元，三个检查存储单元和耦合到三个数据的阵列控制器和三个检查存储单元的数据存储子系统可以容忍任何三个数据的故障，并且检查存储单元可能在存储在数据存储子系统丢失。信息作为对称的最大距离分离码存储在数据存储子系统上，例如Winograd码，里德所罗门码，EVENODD码或EVENODD码的导数。阵列控制器确定检查存储单元的内容，使得数据存储单元和检查存储单元的任何三个擦除可以由阵列控制器校正。阵列控制器仅使用六个IO操作来更新包含在任何一个数据存储单元和检查存储单元中的数据块。

5. 发明授权

US5638065A Maximum-likelihood symbol detection for RLL-coded data 失效
标题翻译： RLL编码数据的最大似然符号检测
公开(公告)号：US5638065A
公开(公告)日：1997-06-10
申请号：US489863
申请日：1995-06-13
申请人： Martin A. Hassner , Tetsuya Tamura , Shmuel Winograd
发明人： Martin A. Hassner , Tetsuya Tamura , Shmuel Winograd
IPC分类号： G11B20/10 , G11B20/14 , G11B20/18 , H03M7/00
CPC分类号： G11B20/1426 , G11B20/10009
摘要： Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.
摘要翻译： RLL编码信道中的模拟信号的并行ML处理，其中（1）信道的当前状态的向量和信道的下一状态的矢量使用模拟信号的沃尔什变换矢量系数来计算; （2）当前状态矢量和下一状态向量以及在模拟匹配滤波器中预先计算的矢量值用于产生与预选阈值进行比较的矢量标量积，用于产生在数字顺序有限状态机中使用的二进制判决输出以产生ML 符号决定（3）ML符号决定被反馈并用于从下一状态的向量中减去当前状态向量的符号间干扰值，以将下一状态向量变换为更新的当前状态向量。

6. 发明授权

US07131052B2 Algebraic decoder and method for correcting an arbitrary mixture of burst and random errors 有权
标题翻译：代数解码器和校正任意混合脉冲串和随机误差的方法
公开(公告)号：US07131052B2
公开(公告)日：2006-10-31
申请号：US10217728
申请日：2002-08-12
申请人： Martin Aureliano Hassner , Tetsuya Tamura , Barry Marshall Trager , Shmuel Winograd
发明人： Martin Aureliano Hassner , Tetsuya Tamura , Barry Marshall Trager , Shmuel Winograd
IPC分类号： H03M13/03
CPC分类号： G11B20/1833
摘要： An error correction algebraic decoder and an associated method correct a combination of a B-byte burst of errors and t-byte random errors in a failed sector, by iteratively adding and removing an erasure (N−B) times until the entire failed sector has been scanned, provided the following inequality is satisfied: (B+2t)≦(R−1), where N denotes the number of bytes, B denotes the length of the burst of errors, t denotes the total number of random errors, and R denotes the number of check bytes in the failed sector. This results in a corrected sector at a decoding latency that is a generally linear function of the number of the check bytes R, as follows: Decoding Latency=5R(N−B).
摘要翻译：错误校正代数解码器和相关联的方法通过迭代地添加和去除擦除（NB）次直到整个故障扇区被扫描来校正错误扇区中的B字节突发和t字节随机错误的组合（B + 2t）<=（R-1），其中N表示字节数，B表示错误突发的长度，t表示随机误差的总数，R表示R 表示故障扇区中的校验字节数。这导致在解码延迟处的校正扇区，其是校验字节R的数量的大致线性函数，如下：解码延迟= 5R（N-B）。

7. 发明授权

US07134066B2 Generalized parity stripe data storage array 失效
标题翻译：广义奇偶条纹数据存储阵列
公开(公告)号：US07134066B2
公开(公告)日：2006-11-07
申请号：US10689814
申请日：2003-10-20
申请人： Martin Aureliano Hassner , Steven R. Hetzler , Tetsuya Tamura , Barry Marshall Trager , Shmuel Winograd
发明人： Martin Aureliano Hassner , Steven R. Hetzler , Tetsuya Tamura , Barry Marshall Trager , Shmuel Winograd
IPC分类号： G11C29/52 , G11C29/42
CPC分类号： H03M13/2909 , G06F11/1076 , H03M13/134 , H03M13/2906
摘要： The Hamming distance of an array of storage devices is increased by generating a parity check matrix based on column equations that are formed using an orthogonal parity code and includes a higher-order multiplier that changes each column. The higher order multiplier is selected to generate a finite basic field of a predetermined number of elements. The array has M rows and N columns, such that M is greater than or equal to three and N is greater than or equal to three. Row 1 through row M−2 of the array each have n–p data storage devices and p parity storage devices. Row M−1 of the array has n−(p+1) data storage devices and (p+1) parity storage devices. Lastly, row M of the array has N parity storage devices.
摘要翻译：存储装置阵列的汉明距离通过基于使用正交奇偶校验码形成的列方程生成奇偶校验矩阵而增加，并且包括改变每列的高阶乘法器。选择较高阶乘数以产生预定数量的元素的有限基本场。阵列具有M行和N列，使得M大于或等于3，N大于或等于3。阵列的行1至行M-2各自具有n-p个数据存储设备和p个奇偶校验存储设备。该阵列的行M-1具有n（p + 1）数据存储设备和（p + 1）奇偶校验存储设备。最后，数组的行M具有N个奇偶校验存储设备。

8. 发明授权

US08171377B2 System to improve memory reliability and associated methods 有权
标题翻译：系统提高内存可靠性和相关方法
公开(公告)号：US08171377B2
公开(公告)日：2012-05-01
申请号：US12023374
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , G06F11/1044 , H03M13/1515
摘要： A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.
摘要翻译：一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统，并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。来自码字的至少两个符号被分配给每个存储器芯片，因此任何存储器芯片的故障可能影响两个或更多个符号。该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表，因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。误差控制编码器能够校正和/或检测更多的误差，如果在表中只有一部分芯片被注意为具有故障，而不是被称为具有故障的全芯片。

9. 发明授权

US07350126B2 Method for constructing erasure correcting codes whose implementation requires only exclusive ORs 有权
标题翻译：用于构造擦除纠正码的方法，其执行仅需要异或
公开(公告)号：US07350126B2
公开(公告)日：2008-03-25
申请号：US10600593
申请日：2003-06-23
申请人： Shmuel Winograd , Barry Marshall Trager
发明人： Shmuel Winograd , Barry Marshall Trager
IPC分类号： H03M13/00
CPC分类号： G06F11/1076 , H03M13/134 , H03M13/1515 , H03M13/373 , H03M13/616 , H03M13/6569
摘要： Error correcting codes of any distance (including codes of distance greater than four) use only exclusive OR (XOR) operations. Any code over a finite field of characteristic two are converted into a code whose encoding and correcting algorithms involve only XORs of words (and loading and storing of the data). Thus, the implementation of the encoding and correcting algorithms is more efficient, since it uses only XORs of words—an operation which is available on almost all microprocessors. An important code, the (3, 3) code of distance four, is also described.
摘要翻译：任何距离（包括距离大于4的码）的纠错码仅使用异或（XOR）操作。特征2的有限域上的任何代码被转换成代码，其编码和校正算法仅涉及字的异或（并且加载和存储数据）。因此，编码和校正算法的实现更有效，因为它仅使用字的异或 - 几乎所有微处理器都可用的操作。还描述了一个重要的代码，即距离四的（3，3）代码。

10. 发明授权

US06792569B2 Root solver and associated method for solving finite field polynomial equations 失效
标题翻译：求解有限域多项式方程的根解和相关方法
公开(公告)号：US06792569B2
公开(公告)日：2004-09-14
申请号：US09842244
申请日：2001-04-24
申请人： Charles Edwin Cox , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
发明人： Charles Edwin Cox , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
IPC分类号： H03M1300
CPC分类号： H03M13/1545 , H03M13/1515
摘要： An error correction algebraic decoder uses a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, and lends itself to efficient hardware implementation and low latency direction calculation. The decoder generally uses a two-step process. The first step is the conversion of quintic equations into sextic equations, and the second step is the adoption of an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix. The second step defines a specific Gaussian elimination that separates the problem of solving quintic and sextic polynomial equations into a simpler problem of finding roots of a quadratic equation and a quartic equation.
摘要翻译：纠错代数解码器使用密钥方程求解器来计算六个有限域多项式方程的根，并适用于有效的硬件实现和低延迟方向计算。解码器通常采用两步法。第一步是将五次方程转换为性别方程，第二步是采用可逆的Tschirnhausen变换，通过消除5度项来减少性别方程。 Tschirnhausen变换的应用大大降低了将多项式方程转换为矩阵所需的操作的复杂性。第二步定义了一个特定的高斯消除，将解决五元和多项式多项式方程的问题分解成找到二次方程和四次方程的根的一个更简单的问题。

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