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    • 3. 发明授权
    • Root solver and associated method for solving finite field polynomial equations
    • 求解有限域多项式方程的根解和相关方法
    • US06792569B2
    • 2004-09-14
    • US09842244
    • 2001-04-24
    • Charles Edwin CoxMartin Aureliano HassnerBarry Marshall TragerShmuel Winograd
    • Charles Edwin CoxMartin Aureliano HassnerBarry Marshall TragerShmuel Winograd
    • H03M1300
    • H03M13/1545H03M13/1515
    • An error correction algebraic decoder uses a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, and lends itself to efficient hardware implementation and low latency direction calculation. The decoder generally uses a two-step process. The first step is the conversion of quintic equations into sextic equations, and the second step is the adoption of an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix. The second step defines a specific Gaussian elimination that separates the problem of solving quintic and sextic polynomial equations into a simpler problem of finding roots of a quadratic equation and a quartic equation.
    • 纠错代数解码器使用密钥方程求解器来计算六个有限域多项式方程的根,并适用于有效的硬件实现和低延迟方向计算。 解码器通常采用两步法。 第一步是将五次方程转换为性别方程,第二步是采用可逆的Tschirnhausen变换,通过消除5度项来减少性别方程。 Tschirnhausen变换的应用大大降低了将多项式方程转换为矩阵所需的操作的复杂性。 第二步定义了一个特定的高斯消除,将解决五元和多项式多项式方程的问题分解成找到二次方程和四次方程的根的一个更简单的问题。
    • 9. 发明授权
    • System to improve memory reliability and associated methods
    • 系统提高内存可靠性和相关方法
    • US08171377B2
    • 2012-05-01
    • US12023374
    • 2008-01-31
    • Timothy J. DellLuis A. Lastras-MontanoBarry M. TragerShmuel Winograd
    • Timothy J. DellLuis A. Lastras-MontanoBarry M. TragerShmuel Winograd
    • G11C29/00
    • H03M13/1545G06F11/1044H03M13/1515
    • A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.
    • 一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统,并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。 来自码字的至少两个符号被分配给每个存储器芯片,因此任何存储器芯片的故障可能影响两个或更多个符号。 该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表,因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。 误差控制编码器能够校正和/或检测更多的误差,如果在表中只有一部分芯片被注意为具有故障,而不是被称为具有故障的全芯片。
    • 10. 发明申请
    • RAID 3 + 3
    • US20080016413A1
    • 2008-01-17
    • US11747887
    • 2007-05-11
    • Steven HetzlerDaniel SmithShmuel Winograd
    • Steven HetzlerDaniel SmithShmuel Winograd
    • G06F11/00
    • G06F11/1076G06F2211/1057G06F2211/1059G06F2211/1064
    • A data storage subsystem that includes three data storage units, three check storage units, and an array controller coupled to the three data and three check storage units can tolerate failure of any three data and check storage units failures can be occur before data stored on the data storage subsystem is lost. Information is stored on the data storage subsystem as a symmetric Maximum Distance Separation code, such as a Winograd code, a Reed Solomon code, an EVENODD code or a derivative of an EVENODD code. The array controller determines the contents of the check storage units so that any three erasures of the data storage units and the check storage units can be corrected by the array controller. The array controller updates a block of data contained in any one of the data storage units and the check storage units using only six IO operations.
    • 包含三个数据存储单元,三个检查存储单元和耦合到三个数据的阵列控制器和三个检查存储单元的数据存储子系统可以容忍任何三个数据的故障,并且检查存储单元可能在存储在 数据存储子系统丢失。 信息作为对称的最大距离分离码存储在数据存储子系统上,例如Winograd码,里德所罗门码,EVENODD码或EVENODD码的导数。 阵列控制器确定检查存储单元的内容,使得数据存储单元和检查存储单元的任何三个擦除可以由阵列控制器校正。 阵列控制器仅使用六个IO操作来更新包含在数据存储单元和检查存储单元中的任何一个中的数据块。