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1. 发明授权

US6057250A Low temperature reflow dielectric-fluorinated BPSG 失效
标题翻译：低温回流电介质氟化BPSG
公开(公告)号：US6057250A
公开(公告)日：2000-05-02
申请号：US14431
申请日：1998-01-27
申请人： Markus Kirchhoff , Ashima Chakravarti , Matthias Ilg , Kevin A. McKinley , Son V. Nguyen , Michael J. Shapiro
发明人： Markus Kirchhoff , Ashima Chakravarti , Matthias Ilg , Kevin A. McKinley , Son V. Nguyen , Michael J. Shapiro
IPC分类号： H01L21/31 , C23C16/40 , H01L21/316 , H01L21/225 , H01L21/469
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02131 , H01L21/02211 , H01L21/31625 , H01L21/31629
摘要： An apparatus and method are provided for forming a fluorine doped borophosphosilicate (F-BPSG) glass on a semiconductor device using a low pressure chemical vapor deposition process. The F-BPSG glass exhibits a substantially void-free and particle-free layer on the substrate for structures having gaps as narrow as 0.10 microns and with aspect ratios of 6:1. The reactant gases include sources of boron and phosphorous dopants, oxygen and a mixture of TEOS and FTES. Using a mixture of TEOS and FTES in a low pressure CVD process provides a F-BPSG layer having the above enhanced characteristics. It is a preferred method of the invention to perform the deposition at a temperature of about 750-850.degree. C. and a pressure of 1 to 3 torr to provide for in situ reflow of the F-BPSG during the deposition process. An anneal is also preferred under similar conditions in the same chemical vapor deposition chamber to further planarize the F-BPSG surface. A F-BPSG glass and semiconductor wafers having a layer of fluorine doped BPSG thereon formed by the method and apparatus of the invention are also provided.
摘要翻译：提供了一种用于在半导体器件上使用低压化学气相沉积工艺形成氟掺杂硼磷硅酸（F-BPSG）玻璃的装置和方法。 F-BPSG玻璃在基板上表现出基本上无空隙和无颗粒的层，其结构具有窄至0.10微米的间隙，纵横比为6:1。反应物气体包括硼和磷掺杂剂的源，氧和TEOS和FTES的混合物。在低压CVD工艺中使用TEOS和FTES的混合物提供具有上述增强特性的F-BPSG层。本发明的优选方法是在约750-850℃的温度和1至3托的压力下进行沉积，以在沉积过程中提供F-BPSG的原位回流。在相同的化学气相沉积室中的相似条件下还优选退火以进一步平坦化F-BPSG表面。还提供了通过本发明的方法和装置形成的具有氟掺杂BPSG层的F-BPSG玻璃和半导体晶片。

2. 发明授权

US5807792A Uniform distribution of reactants in a device layer 失效
标题翻译：反应物在器件层中的均匀分布
公开(公告)号：US5807792A
公开(公告)日：1998-09-15
申请号：US768826
申请日：1996-12-18
申请人： Matthias Ilg , Markus Kirchhoff , Christoph Werner
发明人： Matthias Ilg , Markus Kirchhoff , Christoph Werner
IPC分类号： H01L21/683 , C23C16/44 , C23C16/455 , C30B25/14 , H01L21/205 , H01L21/31 , H01L21/316
CPC分类号： H01L21/02271 , C23C16/44 , C23C16/455 , C30B25/14 , H01L21/02129 , H01L21/31625
摘要： A method and apparatus for forming a multi-constituent device layer on a wafer surface are disclosed. The multi-constituent device layer is formed by flowing a first chemistry comprising a first constituent and a second chemistry comprising a second constituent via a segmented delivery system into a reaction chamber. The reaction chamber comprises a susceptor for supporting and rotating the wafers. The segmented delivery system comprises alternating first and second segments into which the first and second chemistries, respectively, are flowed. The first segments comprise an area that is greater than an area of the second segments by an amount sufficient to effectively reduce the diffusion path of the first constituent. Reducing the diffusion path of the first constituent results in a more uniform distribution of the first constituent within the device layer.
摘要翻译：公开了一种用于在晶片表面上形成多组分器件层的方法和装置。通过将包含第一组分的第一化学物质和包含第二组分的第二化学物质通过分段递送系统流入反应室而形成多构成器件层。反应室包括用于支撑和旋转晶片的基座。分段递送系统包括交替的第一和第二段，第一和第二化学物质分别流入其中。第一段包括大于第二段的面积的面积，其量足以有效地减小第一组分的扩散路径。降低第一组分的扩散路径导致第一组分在器件层内的更均匀分布。

3. 发明授权

US06673693B2 Method for forming a trench in a semiconductor substrate 失效
标题翻译：在半导体衬底中形成沟槽的方法
公开(公告)号：US06673693B2
公开(公告)日：2004-01-06
申请号：US09917554
申请日：2001-07-27
申请人： Markus Kirchhoff
发明人： Markus Kirchhoff
IPC分类号： H01L2176
CPC分类号： H01L21/3063 , H01L21/306 , H01L21/31111 , H01L27/1087 , H01L29/66181
摘要： A method for forming a trench in a semiconductor substrate includes configuring a mask on the substrate. The mask has a window in which a substrate surface is uncovered. The substrate is electrochemically etched proceeding from the substrate surface. A porous substrate is formed in a trench-shaped region proceeding from the substrate surface. The trench is formed by removing the porous substrate from the trench-shaped region.
摘要翻译：在半导体衬底中形成沟槽的方法包括在衬底上配置掩模。掩模具有其中未覆盖基底表面的窗口。从衬底表面电化学蚀刻衬底。在从衬底表面开始的沟槽状区域中形成多孔衬底。通过从沟槽状区域去除多孔基底而形成沟槽。

4. 发明申请

US20050196952A1 Method for production of a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US20050196952A1
公开(公告)日：2005-09-08
申请号：US11065342
申请日：2005-02-25
申请人： Oliver Genz , Markus Kirchhoff , Stefan Machill , Alexander Reb , Barbara Schmidt , Momtchil Stavrev , Maik Stegeman , Stephan Wege
发明人： Oliver Genz , Markus Kirchhoff , Stefan Machill , Alexander Reb , Barbara Schmidt , Momtchil Stavrev , Maik Stegeman , Stephan Wege
IPC分类号： H01L21/027 , H01L21/033 , H01L21/308 , H01L21/311 , H01L21/4763 , H01L21/768 , H01L21/8234 , H01L21/8244
CPC分类号： H01L21/76811 , H01L21/0276 , H01L21/0332 , H01L21/3081 , H01L21/31144
摘要： A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.
摘要翻译：一种制造半导体结构的方法，包括制备半导体衬底，并在所述半导体衬底的表面上产生下部第一，中间第二和上部第三掩模层。该方法还包括在上部第三掩蔽层中形成至少一个第一窗口，使用用于传送第一窗口的第一窗口构造中间第二掩蔽层，使用用于传送第一窗口的第一窗口构造下部第一掩蔽层，以及扩大第一个窗口形成第二个窗口。该方法还包括：使用第二窗口重建中间第二掩蔽层，使用结构化的下部第三掩蔽层，使用第二窗口重构下部第一掩蔽层，并重构半导体衬底，构建半导体衬底; 使用重组的下三层掩蔽层。

5. 发明申请

US20050148193A1 Photolithographic method for forming a structure in a semiconductor substrate 审中-公开
标题翻译：用于在半导体衬底中形成结构的光刻方法
公开(公告)号：US20050148193A1
公开(公告)日：2005-07-07
申请号：US10496102
申请日：2002-11-14
申请人： Markus Kirchhoff , Mirko Vogt , Stephan Wege , Frank Katzwinkel
发明人： Markus Kirchhoff , Mirko Vogt , Stephan Wege , Frank Katzwinkel
IPC分类号： G03F7/09 , H01L21/027 , H01L21/033 , H01L21/308 , H01L21/31 , H01L21/311 , H01L21/312 , H01L21/3213 , H01L21/762 , H01L21/8242
CPC分类号： H01L21/3081 , H01L21/02115 , H01L21/02274 , H01L21/312
摘要： To form a pattern in a semiconductor substrate, a buffer layer, which is formed as a carbon layer, is produced between a photoresist layer and an antireflective layer, which is formed on the substrate. The pattern is produced in the photoresist layer by means of a lithography step, and then it is transferred to the layers arranged below in a subsequent step.
摘要翻译：为了在半导体衬底中形成图案，在形成在衬底上的光致抗蚀剂层和抗反射层之间产生形成为碳层的缓冲层。通过光刻步骤在光致抗蚀剂层中产生图案，然后将其转移到随后的步骤中布置在下面的层中。

6. 发明授权

US06677218B2 Method for filling trenches in integrated semiconductor circuits 有权
标题翻译：在集成半导体电路中填充沟槽的方法
公开(公告)号：US06677218B2
公开(公告)日：2004-01-13
申请号：US10210374
申请日：2002-07-31
申请人： Markus Kirchhoff , Martin Schrems
发明人： Markus Kirchhoff , Martin Schrems
IPC分类号： H01L21762
CPC分类号： H01L27/1087 , H01L21/02238 , H01L21/02258 , H01L21/31675 , H01L21/76224
摘要： A method in which a recess is formed in the surface of a semiconductor substrate and a material is grown on the inner wall of the recess, includes the steps of producing an electrically insulating layer on the surface of the substrate outside the recess, and selectively growing the material on the inner wall of the recess as a result of the substrate, as an electrode, being brought into contact with an electrolysis liquid and electrolysis being carried out, during which the insulating layer prevents the material from growing outside the recess. Before the electrolysis is carried out, a reserve material is epitaxially deposited on the inner wall of the recess and, during the electrolysis, the reserve material is converted into the material being grown by electrolysis.
摘要翻译：一种在半导体衬底的表面上形成凹槽并且在凹部的内壁上生长材料的方法包括以下步骤：在凹部外部的衬底表面上制造电绝缘层，并且选择性地生长作为电极的作为电极的基板的内壁上的材料与电解液体接触并进行电解，在此期间绝缘层防止材料在凹部外生长。在进行电解之前，将储备材料外延地沉积在凹槽的内壁上，并且在电解期间，储备材料被转化为通过电解生长的材料。

7. 发明授权

US06380074B1 Deposition of various base layers for selective layer growth in semiconductor production 有权
标题翻译：在半导体生产中沉积各种基层用于选择性层生长
公开(公告)号：US06380074B1
公开(公告)日：2002-04-30
申请号：US09666526
申请日：2000-09-18
申请人： Markus Kirchhoff , Hans-Peter Sperlich , Uwe Schilling , Zvonimir Gabric , Oswald Spindler , Stephan Wege , Hans Glawischnig
发明人： Markus Kirchhoff , Hans-Peter Sperlich , Uwe Schilling , Zvonimir Gabric , Oswald Spindler , Stephan Wege , Hans Glawischnig
IPC分类号： H01L214763
CPC分类号： H01L21/02129 , H01L21/02304 , H01L21/31612 , H01L21/31625 , H01L21/3185 , H01L21/76262
摘要： A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.
摘要翻译：描述了一种采用半导体电路中的无收缩空穴填充的方法，其利用被施加层的选择性生长。在该方法中，选择性生长材料层同时施加到生长促进层和生长抑制层。其中在施加选择性生长材料层之前至少在其侧面被生长抑制层覆盖的凸起部分。在施加生长抑制层之后，通过各向异性处理在凸起部分之间和之间平行于衬底的表面产生生长促进层，然后再次在凸起部分上平行于衬底的表面上去除该层。该方法使得可以以特别简单的方式产生其隆起部分上的生长抑制层在其侧面和顶部覆盖的图案，而沟槽的底部被生长促进层覆盖。

8. 发明授权

US06759323B2 Method for filling depressions in a surface of a semiconductor structure, and a semiconductor structure filled in this way 有权
标题翻译：用于填充半导体结构的表面中的凹陷的方法，以及以这种方式填充的半导体结构
公开(公告)号：US06759323B2
公开(公告)日：2004-07-06
申请号：US09793345
申请日：2001-02-26
申请人： Markus Kirchhoff
发明人： Markus Kirchhoff
IPC分类号： H01L214763
CPC分类号： H01L21/3185 , C23C16/045 , C23C16/507 , H01L21/3145 , H01L21/31625
摘要： A method for filling depressions in a surface of a semiconductor structure, and a semiconductor structure filled in this way. On a semiconductor structure, in depressions on the surface, in particular below the first metal structure plane, a diffusion barrier layer is deposited, preferably with the aid of plasma-enhanced vapor phase deposition, during which the ions contained in the plasma are accelerated perpendicularly to the surface, resulting in non-conformal deposition of the diffusion barrier layer.
摘要翻译：一种用于填充半导体结构的表面中的凹陷的方法，以及以这种方式填充的半导体结构。在半导体结构上，在表面的凹陷中，特别是在第一金属结构平面下方，优选地，借助于等离子体增强的气相沉积，沉积扩散阻挡层，在该期间，包含在等离子体中的离子垂直加速导致扩散阻挡层的非共形沉积。

9. 发明授权

US06483172B1 Semiconductor device structure with hydrogen-rich layer for facilitating passivation of surface states 有权
标题翻译：具有富氢层的半导体器件结构，用于促进表面状态的钝化
公开(公告)号：US06483172B1
公开(公告)日：2002-11-19
申请号：US09562217
申请日：2000-04-28
申请人： Donna Rizzone Cote , William Joseph Cote , Son Van Nguyen , Markus Kirchhoff , Max G. Levy , Manfred Hauf
发明人： Donna Rizzone Cote , William Joseph Cote , Son Van Nguyen , Markus Kirchhoff , Max G. Levy , Manfred Hauf
IPC分类号： H01L2358
CPC分类号： H01L27/10873 , H01L21/28176 , H01L21/3003 , H01L21/3145 , H01L27/10861
摘要： A process for fabricating a device including the step of forming a structure for facilitating the passivation of surface states is disclosed. The structure comprises an oxynitride layer formed as part of the device structure. The oxynitride facilitates the passivation of surface states when heated.
摘要翻译：公开了一种用于制造包括形成用于促进表面状态的钝化的结构的步骤的装置的方法。该结构包括形成为器件结构的一部分的氧氮化物层。氧氮化物有助于加热时钝化表面状态。

10. 发明授权

US07078313B2 Method for fabricating an integrated semiconductor circuit to prevent formation of voids 失效
标题翻译：用于制造集成半导体电路以防止形成空隙的方法
公开(公告)号：US07078313B2
公开(公告)日：2006-07-18
申请号：US10237543
申请日：2002-09-09
申请人： Markus Kirchhoff
发明人： Markus Kirchhoff
IPC分类号： H01L21/76
CPC分类号： H01L21/76831 , H01L21/76224 , H01L21/7682 , H01L21/76897
摘要： Recesses between gate layer stacks are filled with a first electrically insulating material. Cavities or voids are opened up during the removal of a portion of the first insulating material. These voids are filled during the application of a conductive layer and can then lead to short circuits. Inventively, a layer for closing up voids is produced before the conductive material is applied, as a result of growing a second electrically insulating material onto the surface of the remaining first insulating material. This second insulating layer closes up voids that have formed in the first insulating material so that they can no longer lead to short circuits. In particular, voids that are difficult to gain access to and open out into side walls of contact holes can in this way be closed up in a simple manner.
摘要翻译：栅层堆叠之间的凹陷填充有第一电绝缘材料。在去除第一绝缘材料的一部分期间，开孔或空隙。这些空隙在施加导电层期间被填充，然后可能导致短路。本发明的目的是在施加导电材料之前产生用于封闭空隙的层，这是由于将第二电绝缘材料生长到剩余的第一绝缘材料的表面上。该第二绝缘层闭合在第一绝缘材料中形成的空隙，使得它们不再导致短路。特别是，以这种方式可以以简单的方式闭合难以进入和打开到接触孔的侧壁中的空隙。

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