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1. 发明授权

US06410956B1 Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices 有权
标题翻译：使用间隔物补偿植入物损伤并减少闪存装置中的横向扩散的方法和系统
公开(公告)号：US06410956B1
公开(公告)日：2002-06-25
申请号：US09478864
申请日：2000-01-07
申请人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
发明人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
IPC分类号： H01L2976
CPC分类号： H01L29/66825
摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.
摘要翻译：公开了一种在半导体上提供存储单元的系统和方法。在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。至少一个栅极堆叠具有边缘。所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入存放至少一个栅极堆叠具有边缘。所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个在间隔物沉积之后在半导体中的漏极注入。至少一个门具有边缘。所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

2. 发明授权

US6025240A Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices 失效
公开(公告)号：US6025240A
公开(公告)日：2000-02-15
申请号：US993600
申请日：1997-12-18
申请人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
发明人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825
摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

3. 发明授权

US06168637A Use of a large angle implant and current structure for eliminating a critical mask in flash memory processing 失效
标题翻译：使用大角度注入和电流结构来消除闪存处理中的关键掩模
公开(公告)号：US06168637A
公开(公告)日：2001-01-02
申请号：US08991322
申请日：1997-12-16
申请人： Mark Randolph , Timothy J. Thurgate , Scott D. Luning
发明人： Mark Randolph , Timothy J. Thurgate , Scott D. Luning
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , Y10T29/41
摘要： A method and system for providing a flash memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing a plurality of gate stacks and providing a drain implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the drain implant from reaching the plurality of source areas. In another aspect, the method and system include providing a plurality of gate stacks and providing a source implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the source implant from reaching the plurality of drain areas.
摘要翻译：公开了一种用于在半导体上提供闪存单元的方法和系统。在一个方面，该方法和系统包括提供多个栅极堆叠并以一定角度提供漏极注入。多个栅极堆叠限定多个漏极区域和多个源极区域。该角度是从垂直于半导体表面的方向测量的。该角度允许多个栅极堆叠阻挡漏极植入物到达多个源极区域。在另一方面，该方法和系统包括提供多个栅极叠层并以一定角度提供源植入物。多个栅极堆叠限定多个漏极区域和多个源极区域。该角度是从垂直于半导体表面的方向测量的。该角度允许多个栅极堆叠阻挡源植入物到达多个漏极区域。

4. 发明授权

US6015736A Method and system for gate stack reoxidation control 失效
标题翻译：栅堆叠再氧化控制方法与系统
公开(公告)号：US6015736A
公开(公告)日：2000-01-18
申请号：US993787
申请日：1997-12-19
申请人： Scott D. Luning , Mark Randolph
发明人： Scott D. Luning , Mark Randolph
IPC分类号： H01L21/28 , H01L21/26
CPC分类号： H01L21/28273 , Y10S438/911 , Y10T29/41
摘要： A system and method for providing at least one memory cell on a semiconductor is disclosed. The method and system include providing a tunneling barrier on the semiconductor, providing at least one floating gate having a corner, and oxidizing the tunneling barrier, a portion of the semiconductor, and the at least one floating gate. A portion of the at least one floating gate including the corner is disposed above the tunneling barrier. The portion of the semiconductor oxidizes at a first rate and at least the corner of the at least one floating gate oxidizes at a second rate. The second rate is sufficiently higher than the first rate to provide a desired thickness of the tunneling barrier a distance from the corner of the at least one floating gate for a particular rounding of the corner of the at least one floating gate.
摘要翻译：公开了一种在半导体上提供至少一个存储单元的系统和方法。所述方法和系统包括在半导体上提供隧道势垒，提供至少一个具有拐角的浮动栅极，以及氧化隧道势垒，半导体的一部分和至少一个浮动栅极。包括拐角的至少一个浮动栅极的一部分设置在隧道势垒上方。半导体的部分以第一速率氧化，并且至少一个浮栅的至少角部以第二速率氧化。第二速率足够高于第一速率，以便为至少一个浮动门的拐角的特定四舍五入提供距离至少一个浮动栅极的角的距离的隧道势垒的期望厚度。

5. 发明授权

US6127222A Non-self-aligned side channel implants for flash memory cells 失效
标题翻译：用于闪存单元的非自对准侧通道植入物
公开(公告)号：US6127222A
公开(公告)日：2000-10-03
申请号：US991687
申请日：1997-12-16
申请人： Scott D. Luning , Mark Randolph
发明人： Scott D. Luning , Mark Randolph
IPC分类号： H01L21/336
CPC分类号： H01L29/66825
摘要： A system and method for providing a flash memory cell on a semiconductor substrate are disclosed. The system and method include providing a side implant and providing an implant in at least one of a drain or a source of the flash memory cell.
摘要翻译：公开了一种用于在半导体衬底上提供闪存单元的系统和方法。该系统和方法包括提供侧植入物并在闪速存储器单元的漏极或源极中的至少一个中提供植入物。

6. 发明授权

US09732321B2 Engineered craniofacial constructs with composite scaffold 有权
公开(公告)号：US09732321B2
公开(公告)日：2017-08-15
申请号：US13028725
申请日：2011-02-16
申请人： Erik Bassett , Mack Cheney , Theresa Hadlock , Irina Pomerantseva , Mark Randolph , Cathryn Sundback , Joseph Vacanti
发明人： Erik Bassett , Mack Cheney , Theresa Hadlock , Irina Pomerantseva , Mark Randolph , Cathryn Sundback , Joseph Vacanti
IPC分类号： A61F2/02 , C12N5/077 , A61L27/04 , A61L27/24 , A61L27/50 , C12N5/0775
CPC分类号： C12N5/0655 , A61L27/04 , A61L27/24 , A61L27/50 , C12N5/0663 , C12N2501/15 , C12N2502/1317 , C12N2533/54
摘要： The present invention provides for compositions and constructs for craniofacial reconstruction implants, and methods for making and using same. Specific embodiments provide for a biocompatible scaffold having an auricular shape and a permanent bendable framework within the scaffold, wherein the permanent bendable framework allows deformation and return to pre-deformation shape, and thus maintains the auricular shape of the scaffold.

7. 发明申请

US20130158342A1 PHOTOCHEMICAL TISSUE BONDING 审中-公开
标题翻译：化学组织结合
公开(公告)号：US20130158342A1
公开(公告)日：2013-06-20
申请号：US13543137
申请日：2012-07-06
申请人： Barbara Chan , Timothy Shane Johnson , Irene E. Kochevar , Mark Randolph , Robert W. Redmond , Jonathan M. Winograd
发明人： Barbara Chan , Timothy Shane Johnson , Irene E. Kochevar , Mark Randolph , Robert W. Redmond , Jonathan M. Winograd
IPC分类号： A61B17/11
CPC分类号： A61B17/11 , A61B2017/00508 , A61B2017/00517 , A61F9/0079 , A61F9/0081 , A61F9/00821 , A61F2009/00842 , A61F2009/00853 , A61F2009/00872 , A61F2009/00887 , A61L24/001 , A61L2430/32 , A61N5/062
摘要： Photochemical tissue boding methods for bonding neural tissues include the application of a photosensitizer to a tissue and/or tissue graft, followed by irradiation with electromagnetic energy to produce a tissue seal. The methods are useful for tissue adhesion, such as in wound closure, tissue grafting, skin grafting, musculoskeletal tissue repair, ligament or tendon repair, neural repair, blood vessel repair and corneal repair.
摘要翻译：用于粘合神经组织的光化学组织编织方法包括将光敏剂施用于组织和/或组织移植物，随后用电磁能照射以产生组织密封。该方法可用于组织粘连，例如伤口闭合，组织移植，皮肤移植，肌肉骨骼组织修复，韧带或肌腱修复，神经修复，血管修复和角膜修复。

8. 发明授权

US07492001B2 High K stack for non-volatile memory 有权
标题翻译：高K堆栈用于非易失性存储器
公开(公告)号：US07492001B2
公开(公告)日：2009-02-17
申请号：US11086310
申请日：2005-03-23
申请人： Wei Zheng , Mark Randolph , Hidehiko Shiraiwa
发明人： Wei Zheng , Mark Randolph , Hidehiko Shiraiwa
IPC分类号： H01L29/788 , H01L29/72
CPC分类号： H01L29/792 , G11C16/0475 , H01L21/28273 , H01L21/28282
摘要： A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.
摘要翻译：存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极形成在电介质材料层上。

9. 发明授权

US07402868B2 System and method for protecting semiconductor devices 有权
标题翻译：用于保护半导体器件的系统和方法
公开(公告)号：US07402868B2
公开(公告)日：2008-07-22
申请号：US10976816
申请日：2004-11-01
申请人： Ihsan Jahed Djomehri , Mark Randolph , Yi He , Wei Zheng
发明人： Ihsan Jahed Djomehri , Mark Randolph , Yi He , Wei Zheng
IPC分类号： H01L23/62
CPC分类号： H01L27/115 , H01L27/0288
摘要： A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device.
摘要翻译：半导体存储器件包括一组字线和被配置成在制造半导体存储器件期间消散来自字线组的电流的结构。

10. 发明授权

US07206224B1 Methods and systems for high write performance in multi-bit flash memory devices 有权
公开(公告)号：US07206224B1
公开(公告)日：2007-04-17
申请号：US11037477
申请日：2005-01-18
申请人： Mark Randolph , Darlene Hamilton , Roni Kornitz
发明人： Mark Randolph , Darlene Hamilton , Roni Kornitz
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/10 , G11C2211/5641
摘要： Methods and circuits for performing high speed write (programming) operations in a dual-bit flash memory array. The method includes, for example, erasing a first and second bit of each cell in the array to a first state, programming the first bit of each cell in the array to a second state, and subsequently programming the second bit of one or more cells in the array to one of the first and second state according to the user's data, resulting in fast write (programming) of those second bits. In addition, the circuit includes, for example, a core cell array having dual-bit flash memory cells configured into a plurality of array portions. The circuit further includes a control circuit configured to selectively block erase one of the array portions, wherein in a first phase of the block erase both first and second bit locations of each dual-bit flash memory cell in the one array portion have sufficient charge removed therefrom to achieve a first state. The control circuit is further configured to, in a second phase of the block erase, supply charge to the first bit location of each dual-bit flash memory cell of the one array portion to enable subsequently fast-write of user's data to the second bit location.

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