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1. 发明授权

US06043533A Method of integrating Ldd implantation for CMOS device fabrication 失效
标题翻译：整合Ldd植入用于CMOS器件制造的方法
公开(公告)号：US06043533A
公开(公告)日：2000-03-28
申请号：US944377
申请日：1997-10-06
申请人： Mark I. Gardner , Fred Hause , Robert Paiz
发明人： Mark I. Gardner , Fred Hause , Robert Paiz
IPC分类号： H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of integrating lightly doped drain implantation for complementary metal oxide semiconductor (CMOS) device fabrication includes providing a semiconductor substrate having a p-well region and an n-well region. A patterned gate oxide and gate electrode are formed on each of the p-well region and the n-well region. One of either the p-well region or the n-well region is masked with a patterned photoresist having a prescribed thickness, leaving a non-masked region exposed. Ions are then implanted to form desired p-type lightly doped drain (Pldd) regions in the n-well region, including Pldd regions adjacent to edges of the gate electrode in the n-well region. Lastly, ions are implanted to form desired n-type lightly doped drain (Nldd) regions in the p-well region, including Nldd regions adjacent to edges of the gate electrode in the p-well region, the Pldd and Nldd regions thus being formed with the use of only a single ion implantation masking step. A semiconductor substrate and an integrated circuit are also disclosed.
摘要翻译：用于互补金属氧化物半导体（CMOS）器件制造的轻掺杂漏极注入的集成方法包括提供具有p阱区域和n-阱区域的半导体衬底。在p阱区域和n阱区域中的每一个上形成图案化栅极氧化物和栅极电极。使用具有规定厚度的图案化光致抗蚀剂掩蔽p阱区域或n阱区域中的一个，留下未被掩蔽的区域。然后植入离子以在n阱区域中形成期望的p型轻掺杂漏极（Pldd）区域，包括与n阱区域中的栅电极的边缘相邻的Pldd区域。最后，注入离子以在p阱区域中形成期望的n型轻掺杂漏极（Nldd）区域，包括与p阱区域中的栅电极的边缘相邻的Nldd区域，从而形成Pldd和Nldd区域仅使用单个离子注入掩模步骤。还公开了半导体衬底和集成电路。

2. 发明授权

US6148832A Method and apparatus for in-situ cleaning of polysilicon-coated quartz furnaces 失效
标题翻译：用于多晶硅涂层石英炉原位清洗的方法和装置
公开(公告)号：US6148832A
公开(公告)日：2000-11-21
申请号：US145606
申请日：1998-09-02
申请人： Mark C. Gilmer , Mark I. Gardner , Robert Paiz
发明人： Mark C. Gilmer , Mark I. Gardner , Robert Paiz
IPC分类号： B08B9/093 , C11D7/08 , C11D7/32 , C11D7/50 , C11D11/00 , B08B3/02 , B08B9/00
CPC分类号： C11D7/08 , B08B9/093 , C11D11/0041 , C11D7/5013 , C11D7/3209
摘要： An apparatus for in-situ cleaning of polysilicon-coated quartz furnaces are presented. Traditionally, disassembling and reassembling the furnace is required to clean the quartz. This procedure requires approximately four days of down time which can be very costly for a company. In addition, cleaning the quartz requires large baths filled with a cleaning agent. These baths occupy a large amount of laboratory space and require a large amount of the cleaning agent. Cleaning the furnace in-situ eliminates the very time consuming procedure of assembling and disassembling the furnace and at the same time requires less laboratory space and less amount of cleaning agent. The polysilicon remover may be either a mixture of hydrofluoric and nitric acid or TMAH. TMAH is preferred because it less hazardous than hydrofluoric acid and compatible with more materials. The cleaning agent may be introduced into the furnace either from the built-in injectors or from additionally installed injectors. If the built-in injectors are used, the input system of the furnace is cleaned in addition to the quartz inner lining.
摘要翻译：介绍了一种用于原位清洗多晶硅涂层石英炉的设备。传统上，需要拆卸和重新组装炉子来清洁石英。该程序需要大约四天的停机时间，这对公司来说可能是非常昂贵的。此外，清洁石英需要大量的填充有清洁剂的浴池。这些浴室占据大量的实验室空间，需要大量的清洁剂。原地清洗炉子消除了组装和拆卸炉子非常耗时的过程，同时需要更少的实验室空间和更少量的清洁剂。多晶硅去除剂可以是氢氟酸和硝酸或TMAH的混合物。 TMAH是优选的，因为它比氢氟酸更危险，并且与更多的材料相容。清洁剂可以从内置注射器或另外安装的注射器引入炉中。如果使用内置注射器，除了石英内衬之外，还要清洁炉子的输入系统。

3. 发明授权

US5918133A Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof 失效
标题翻译：半导体器件沿着沟道具有双栅极电介质厚度及其制造
公开(公告)号：US5918133A
公开(公告)日：1999-06-29
申请号：US993029
申请日：1997-12-18
申请人： Mark I. Gardner , Robert Paiz
发明人： Mark I. Gardner , Robert Paiz
IPC分类号： H01L21/265 , H01L21/28 , H01L21/32 , H01L21/336 , H01L29/423 , H01L29/51 , H01L21/31 , H01L21/3115
CPC分类号： H01L21/28202 , H01L21/26506 , H01L21/2822 , H01L21/32 , H01L29/42368 , H01L29/512 , H01L29/518 , H01L29/66659 , H01L21/28194
摘要： Generally, the present invention relates to a semiconductor device having a dual thickness gate dielectric along the channel and a process of fabricating such a device. By providing a dual thickness gate dielectric, the gate dielectric can, for example, be optimized to the transistor and device performance can be enhanced.
摘要翻译：通常，本发明涉及一种具有沿通道的双重厚度栅极电介质的半导体器件和制造这种器件的工艺。通过提供双厚度栅极电介质，栅极电介质例如可以优化到晶体管，并且可以提高器件性能。

4. 发明授权

US06727569B1 Method of making enhanced trench oxide with low temperature nitrogen integration 失效
标题翻译：制备具有低温氮一体化的增强型沟槽氧化物的方法
公开(公告)号：US06727569B1
公开(公告)日：2004-04-27
申请号：US09063081
申请日：1998-04-21
申请人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
发明人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
IPC分类号： H01L2900
CPC分类号： H01L21/76235
摘要： A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into a portion of the trench liner to form an oxynitride layer. After formation of the oxynitride layer, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.
摘要翻译：半导体衬底内的有源区域之间的结构和改进的隔离沟槽包括在硅衬底上形成并在衬垫层上形成氮化物层。此后，在氮化硅层上图案化光致抗蚀剂层，使得随后将形成隔离沟槽的氮化物层的区域被暴露。接下来，蚀刻掉位于氮化物层的暴露区域之下的氮化物层和焊盘层的暴露区域以暴露硅衬底的区域。随后，用干蚀刻工艺将隔离沟槽蚀刻到硅衬底中。然后形成沟槽衬垫，并且氮结合到沟槽衬垫的一部分中以形成氧氮化物层。在形成氮氧化物层之后，用优选由CVD氧化物构成的电介质填充沟槽。此后，CVD填充电介质被平坦化，并且氮化物层被剥离。

5. 发明授权

US6160316A Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths 失效
标题翻译：利用气隙的集成电路来减小相邻金属线宽之间的电容
公开(公告)号：US6160316A
公开(公告)日：2000-12-12
申请号：US34633
申请日：1998-03-04
申请人： Mark I. Gardner , Thomas E. Spikes , Robert Paiz
发明人： Mark I. Gardner , Thomas E. Spikes , Robert Paiz
IPC分类号： H01L21/768 , H01L23/522 , H01L29/72
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming a multi-level interconnect in which capacitive coupling between laterally adjacent conductors employed by an integrated circuit is reduced. According to an embodiment, a conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the conductor. Select portions of the conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the conductor. An interlevel dielectric is deposited to a level above the masking structure such that air gaps are formed laterally adjacent the opposed sidewall surfaces of the conductor, and the interlevel dielectric is planarized to a level spaced above an upper surface of the masking structure.
摘要翻译：提供了一种用于形成多级互连的方法，其中集成电路采用的横向相邻导体之间的电容耦合被减小。根据实施例，导体在半导体衬底上介电间隔开，并且掩模结构布置在导体的上表面上。选择导体的部分被去除，使得掩模结构的相对端延伸超过导体的相对的侧壁表面。将层间电介质沉积到掩蔽结构上方的水平面上，使得气隙横向地邻近导体的相对的侧壁表面形成，并且层间电介质被平坦化为在掩模结构的上表面上方间隔的水平。

6. 发明授权

US5946581A Method of manufacturing a semiconductor device by doping an active region after formation of a relatively thick oxide layer 失效
标题翻译：在形成相对厚的氧化物层之后通过掺杂有源区制造半导体器件的方法
公开(公告)号：US5946581A
公开(公告)日：1999-08-31
申请号：US780644
申请日：1997-01-08
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
IPC分类号： H01L21/336 , H01L21/768
CPC分类号： H01L29/6659 , H01L21/76814
摘要： In a semiconductor device fabrication process, an active region of the semiconductor device is formed by doping an active region after formation of a relatively thick oxide layer. According to the process, a gate electrode is formed on a substrate and a relatively thick oxide layer is formed over the gate electrode. Portions of the relatively thick oxide layer are removed to expose a region of the substrate adjacent the gate electrode. The exposed region is then doped with a dopant to form an active region. The active region may form an LDD region. The relatively thick oxide layer may comprise a contact formation layer.
摘要翻译：在半导体器件制造工艺中，半导体器件的有源区通过在形成相对厚的氧化物层之后掺杂有源区而形成。根据该工序，在基板上形成栅电极，在栅电极上形成较厚的氧化层。去除相对厚的氧化物层的部分以露出与栅电极相邻的衬底的区域。然后用暴露的区域掺杂掺杂剂以形成有源区。有源区域可以形成LDD区域。相对厚的氧化物层可以包括接触形成层。

7. 发明授权

US06194283B1 High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers 失效
标题翻译：由于新的间隔填充方法包括各向异性蚀刻氮化硅间隔物，高密度沟槽填充
公开(公告)号：US06194283B1
公开(公告)日：2001-02-27
申请号：US08959587
申请日：1997-10-29
申请人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
发明人： Mark I. Gardner , Robert Paiz , Thomas E. Spikes, Jr.
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for forming an isolation trench in a semiconductor substrate that is substantially free of voids. The method includes forming a dielectric masking layer above a semiconductor substrate. An opening is preferably formed through the masking layer and partially into the semiconductor substrate forming a shallow trench within the semiconductor substrate. Optionally, thermal oxidation of the trench may be performed to form an oxide layer within the trench. A spacer layer is preferably deposited across the exposed surface of the topography. The spacer layer is preferably etched to form spacers directly adjacent to opposed sidewall surfaces of the trench. The isolation trench may then be filled with an isolation dielectric. The presence of the spacers within the isolation trench preferably causes the lower portions of the trench to fill up faster than the upper portions. In this manner the trench may be filled without the formation of voids.
摘要翻译：一种在半导体衬底中形成基本上没有空隙的隔离沟槽的方法。该方法包括在半导体衬底上形成电介质掩模层。优选地，通过掩模层形成开口，并且部分地形成在半导体衬底内形成浅沟槽的半导体衬底中。可选地，可以进行沟槽的热氧化以在沟槽内形成氧化物层。间隔层优选沉积在地形的暴露表面上。优选蚀刻间隔层以形成与沟槽的相对侧壁表面直接相邻的间隔物。然后可以用隔离电介质填充隔离沟槽。间隔物在隔离沟槽内的存在优选地使得沟槽的下部比上部更快地填充。以这种方式，可以填充沟槽而不形成空隙。

8. 发明授权

US5929496A Method and structure for channel length reduction in insulated gate field effect transistors 失效
标题翻译：绝缘栅场效应晶体管的沟道长度减小的方法和结构
公开(公告)号：US5929496A
公开(公告)日：1999-07-27
申请号：US993767
申请日：1997-12-18
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz
IPC分类号： H01L21/223 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/28194 , H01L21/223 , H01L21/26513 , H01L29/42364 , H01L29/6659
摘要： A method and structure are provided for an IGFET which has a highly scalable short conduction channel length. The short channel IGFET functions more rapidly than do longer conduction channel devices. Lightly doped regions provide a graded extension or buffer region to the conduction channel. Thus, the voltage drop is shared by the source/drain and channel, in contrast to an abrupt n+/p junction where the almost the entire voltage drop occurs across the lightly doped (channel) side of the junction. This method and structure preserves the integrity of the IGFET by protecting the gate from "hot electron injection." The method and structure provide an IGFET with increased performance without compromising the IGFET's reliability or longevity.
摘要翻译：提供了一种IGFET的方法和结构，其具有高度可缩放的短导电沟道长度。短通道IGFET的功能比延长的导通通道器件更快。轻掺杂区域为传导通道提供渐变的延伸或缓冲区域。因此，与突然的n + / p结相比，源/漏和沟道的电压降是共同的，其中几乎整个电压降在结点的轻掺杂（沟道）侧上发生。该方法和结构通过保护栅极免受“热电子注入”的影响来保持IGFET的完整性。该方法和结构提供IGFET具有更高的性能，而不会影响IGFET的可靠性或寿命。

9. 发明授权

US06214123B1 Chemical vapor deposition systems and methods for depositing films on semiconductor wafers 失效
标题翻译：化学气相沉积系统和在半导体晶片上沉积薄膜的方法
公开(公告)号：US06214123B1
公开(公告)日：2001-04-10
申请号：US09137902
申请日：1998-08-20
申请人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
发明人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
IPC分类号： C23C1600
CPC分类号： C23C16/45514 , C23C16/4409 , C23C16/4584
摘要： The present disclosure relates to a chemical vapor deposition system including a chemical vapor deposition chamber, and a circlet wafer positioned within the chemical vapor deposition chamber. The circlet wafer is mounted on a rotatable member that at least partially extends through an opening of the wafer. A drive mechanism is used to rotate the rotatable member and the circlet wafer. The system also includes a gas injector for injecting reactive gases toward the circlet wafer. The present disclosure also relates to a chemical vapor deposition system including a chemical vapor deposition chamber, a wafer positioned within the chemical vapor deposition chamber, and a gas injector for injecting first and second reactive gases toward the wafer. The gas injector includes a mixing region for mixing the first and second reactive gases before the first and second reactive gases are discharged from the gas injector.
摘要翻译：本公开涉及包括化学气相沉积室和位于化学气相沉积室内的圆盘晶片的化学气相沉积系统。小圆片安装在至少部分地延伸穿过晶片的开口的可旋转构件上。使用驱动机构来旋转可旋转构件和小圆片。该系统还包括用于将反应性气体注入到小圆片的气体注射器。本公开还涉及包括化学气相沉积室，位于化学气相沉积室内的晶片的化学气相沉积系统和用于向晶片注入第一和第二反应气体的气体注入器。气体喷射器包括用于在第一和第二反应气体从气体喷射器排出之前混合第一和第二反应气体的混合区域。

10. 发明授权

US6140191A Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions 有权
标题翻译：制造高性能MOSFET的方法，集成同时形成源极/漏极和栅极区域
公开(公告)号：US6140191A
公开(公告)日：2000-10-31
申请号：US157973
申请日：1998-09-21
申请人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
发明人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/66575 , H01L21/823814 , H01L21/823842 , H01L21/2652 , H01L29/66545
摘要： An integrated circuit and a method of making a transistor thereof are provided. The method includes the steps of forming a first stack on the substrate and a second stack on substrate in spaced-apart relation to the first stack, where the first stack has a first layer and first and second spacers adjacent to the first layer and the second stack has a second layer and third and fourth spacers adjacent to the second layer. A gate dielectric layer is formed on the substrate between the first and second stacks and a first conductor layer is formed on the gate dielectric layer. A first source/drain region is formed beneath the first conductor layer and a second source/drain region is formed beneath the second conductor layer. The first and second layers are removed and a first contact is formed on the first source/drain region and a second contact is formed on the second source/drain region. The method integrates gate and source/drain region formation and provides for gate electrodes with work functions tailored for n-channel and p-channel devices.
摘要翻译：提供集成电路及其制造晶体管的方法。该方法包括以下步骤：在衬底上形成第一堆叠，并且在衬底上形成与第一堆叠间隔开的第二叠层，其中第一堆叠具有第一层，第一和第二衬垫与第一层相邻，堆叠具有与第二层相邻的第二层和第三和第四间隔物。在第一和第二堆叠之间的衬底上形成栅极电介质层，并且在栅极电介质层上形成第一导体层。第一源极/漏极区域形成在第一导体层下面，并且第二源极/漏极区域形成在第二导体层下面。去除第一层和第二层，并且在第一源极/漏极区上形成第一接触，并且在第二源极/漏极区上形成第二接触。该方法集成了栅极和源极/漏极区域形成，为门极提供了针对n沟道和p沟道器件定制的工作功能。

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