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1. 发明授权

US09157950B2 Loop parameter sensor using repetitive phase errors 有权
标题翻译：循环参数传感器使用重复相位误差
公开(公告)号：US09157950B2
公开(公告)日：2015-10-13
申请号：US13088949
申请日：2011-04-18
申请人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
发明人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
IPC分类号： G01R25/00 , G01R31/28 , H03L7/093 , H03L7/107 , H03L7/18
CPC分类号： H03L7/085 , G01R31/2824 , H03L7/093 , H03L7/1075 , H03L7/1077 , H03L7/18 , H03L2207/06
摘要： A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.
摘要翻译：公开了用于测量锁相环频率合成器（PLL）中的指定参数的方法和系统。在一个实施例中，该方法包括在PLL中引入多个相位误差，测量所引入的相位误差的特定方面，以及使用引入的相位误差的测量方面来确定所述指定参数的值。在一个实施例中，在PLL中重复地引入相位误差，并且这些相位误差在PPL中产生参考信号和反馈信号之间的修正的相位差。在一个实施例中，当修改的相位差超过预设值时，交叉时间被确定，并且这些交叉时间被用于确定指定参数的值。在一个实施例中，该参数被计算为交叉时间的数学函数。该参数可以是例如PLL的带宽。

2. 发明申请

US20120262149A1 LOOP PARAMETER SENSOR USING REPETITIVE PHASE ERRORS 有权
标题翻译：使用重复相位错误的环路参数传感器
公开(公告)号：US20120262149A1
公开(公告)日：2012-10-18
申请号：US13088949
申请日：2011-04-18
申请人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
发明人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
IPC分类号： G01R25/00
CPC分类号： H03L7/085 , G01R31/2824 , H03L7/093 , H03L7/1075 , H03L7/1077 , H03L7/18 , H03L2207/06
摘要： A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.
摘要翻译：公开了用于测量锁相环频率合成器（PLL）中的指定参数的方法和系统。在一个实施例中，该方法包括在PLL中引入多个相位误差，测量所引入的相位误差的特定方面，以及使用引入的相位误差的测量方面来确定所述指定参数的值。在一个实施例中，在PLL中重复地引入相位误差，并且这些相位误差在PPL中产生参考信号和反馈信号之间的修正的相位差。在一个实施例中，当修改的相位差超过预设值时，交叉时间被确定，并且这些交叉时间被用于确定指定参数的值。在一个实施例中，该参数被计算为交叉时间的数学函数。该参数可以是例如PLL的带宽。

3. 发明授权

US07602869B2 Methods and apparatus for clock synchronization and data recovery in a receiver 有权
标题翻译：接收机中时钟同步和数据恢复的方法和装置
公开(公告)号：US07602869B2
公开(公告)日：2009-10-13
申请号：US11193868
申请日：2005-07-29
申请人： Azita Emami-Neyestanak , Mounir Meghelli , Benjamin D. Parker , Sergey V. Rylov , Alexander V. Rylyakov , Jose A. Tierno
发明人： Azita Emami-Neyestanak , Mounir Meghelli , Benjamin D. Parker , Sergey V. Rylov , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point. Further, for a next sampling cycle, the first clock may be used to sweep through phase positions with respect to the set phase position of the second clock corresponding to the sampling point in the first sampling cycle such that a next sampling point may be determined.
摘要翻译：公开了时钟同步和数据恢复技术。例如，用于同步用于恢复接收到的数据的时钟的技术包括以下步骤/操作。将第一时钟（例如，数据时钟）设置为在接收到的数据中的给定单位间隔内的第一相位位置的第一采样周期。第二时钟（例如，扫描时钟）相对于第一相位位置扫过其它相位位置，从而确定从接收到的数据中的给定单位间隔到另一个单位间隔的转变。基于与第二时钟相关联的相位位置处的测量来确定采样点。将第二时钟设置为对应于采样点的相位位置，使得可以在该采样点恢复数据。此外，对于下一采样周期，可以使用第一时钟相对于与第一采样周期中的采样点对应的第二时钟的设置相位位置扫描相位位置，使得可以确定下一采样点。

4. 发明申请

US20120117413A1 METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs) 失效
标题翻译：方法和基础设施，用于在协调的现场可编程门阵列（FPGA）上的大规模数字电路上进行循环复制仿真
公开(公告)号：US20120117413A1
公开(公告)日：2012-05-10
申请号：US12941834
申请日：2010-11-08
申请人： Sameh W. Asaad , Ralph E. Bellofatto , Bernard Brezzo , Charles L. Haymes , Mohit Kapur , Benjamin D. Parker , Thomas Roewer , Jose A. Tierno
发明人： Sameh W. Asaad , Ralph E. Bellofatto , Bernard Brezzo , Charles L. Haymes , Mohit Kapur , Benjamin D. Parker , Thomas Roewer , Jose A. Tierno
IPC分类号： G06F1/06 , G06F1/04
CPC分类号： G06F1/10 , G06F1/06 , G06F17/5027 , H03K19/17736
摘要： A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.
摘要翻译：多个目标现场可编程门阵列根据目标系统的连接拓扑和地图部分互连。控制模块耦合到多个目标现场可编程门阵列。平衡时钟分配网络被配置为分配参考时钟信号，并且平衡复位分配网络耦合到控制模块并且被配置为将复位信号分配给多个目标现场可编程门阵列。控制模块和平衡复位分配网络协同配置以启动和控制目标系统与多个目标现场可编程门阵列的模拟。多个本地时钟控制状态机驻留在目标现场可编程门阵列中。本地时钟控制状态机耦合到平衡时钟分配网络并从其获得参考时钟信号。多个本地时钟控制状态机被配置为生成一组同步的自由运行和可停止时钟，以维持目标系统的模拟的循环精确和循环可再现的执行。还提供了一种方法。

5. 发明授权

US09002693B2 Wire like link for cycle reproducible and cycle accurate hardware accelerator 有权
标题翻译：线条链接循环可再现和循环精确的硬件加速器
公开(公告)号：US09002693B2
公开(公告)日：2015-04-07
申请号：US13342128
申请日：2012-01-02
申请人： Sameh Asaad , Mohit Kapur , Benjamin D. Parker
发明人： Sameh Asaad , Mohit Kapur , Benjamin D. Parker
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.
摘要翻译：提供了第一和第二现场可编程门阵列，其实现要被模拟的电路设计的第一和第二块。现场可编程门阵列以第一时钟频率操作，并且提供线状链路以在它们之间发送多个信号。线状链路包括在第一现场可编程门阵列上串行化串行化多个信号的串行器; 第二现场可编程门阵列上的解串器，用于反序列化所述多个信号; 以及序列化器和解串器之间的连接。串行器和解串器以大于第一时钟频率的第二时钟频率操作，并且选择第二时钟频率使得多个信号的发送和接收的延迟小于对应于第一时钟频率的周期。

6. 发明授权

US06990161B2 Phase selection mechanism for optimal sampling of source synchronous clocking interface data 失效
公开(公告)号：US06990161B2
公开(公告)日：2006-01-24
申请号：US10044649
申请日：2002-01-09
申请人： Daniel J. Friedman , Benjamin D. Parker
发明人： Daniel J. Friedman , Benjamin D. Parker
IPC分类号： H04L7/00
CPC分类号： G06F5/06 , H04L7/0012 , H04L7/0045 , H04L7/0337
摘要： Phase selection mechanisms for the optimal sampling of data at the receiving end of a SSC interface. The receiver is allowed to choose between several phases of its local clock, to best synchronize the transmitter data to the receiver clock domain. It results in a minimum depth first in first out (FIFO) register to accomplish the handoff of transmit data from the transmit clock to the receive dock. It avoids the requirement of a delay locked loop (DLL) to bring the transmitter clock into a desired phase relationship with respect to the receiver clock. At least one embodiment of the present invention provides a solution specific to the DDR or full rate clocking SSC interface.

7. 发明申请

US20130170525A1 WIRE LIKE LINK FOR CYCLE REPRODUCIBLE AND CYCLE ACCURATE HARDWARE ACCELERATOR 有权
标题翻译：绕线循环可循环硬件加速器
公开(公告)号：US20130170525A1
公开(公告)日：2013-07-04
申请号：US13342128
申请日：2012-01-02
申请人： Sameh Asaad , Mohit Kapur , Benjamin D. Parker
发明人： Sameh Asaad , Mohit Kapur , Benjamin D. Parker
IPC分类号： H04B1/38
CPC分类号： G06F17/5027
摘要： First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.
摘要翻译：提供了第一和第二现场可编程门阵列，其实现要被仿真的电路设计的第一和第二块。现场可编程门阵列以第一时钟频率操作，并且提供线状链路以在它们之间发送多个信号。线状链路包括在第一现场可编程门阵列上串行化串行化多个信号的串行器; 第二现场可编程门阵列上的解串器，用于反序列化所述多个信号; 以及序列化器和解串器之间的连接。串行器和解串器以大于第一时钟频率的第二时钟频率操作，并且选择第二时钟频率使得多个信号的发送和接收的延迟小于对应于第一时钟频率的周期。

8. 发明授权

US06429794B1 Format converter 失效
标题翻译：格式转换器
公开(公告)号：US06429794B1
公开(公告)日：2002-08-06
申请号：US09609048
申请日：2000-06-30
申请人： Albert X. Widmer , Charles L. Haymes , Benjamin D. Parker
发明人： Albert X. Widmer , Charles L. Haymes , Benjamin D. Parker
IPC分类号： H03M900
CPC分类号： H03M9/00
摘要： A format converter in which the data input is a 16 bit wide interface. The circuit finds the 66-bit coding block boundaries. In one embodiment, a circuit presents the 66-bit data blocks at the output in an aligned format. The circuit relies on control inputs from a state machine which controls the operating mode and to which it delivers status information. The two main operating modes are the “normal data” mode or the “hunt” mode for the 66-bit block boundaries.
摘要翻译：格式转换器，其中数据输入是16位宽的接口。该电路找到66位编码块边界。在一个实施例中，电路以对准格式在输出处呈现66位数据块。该电路依赖于来自状态机的控制输入，该状态机控制操作模式并传送状态信息。两种主要操作模式是“正常数据”模式或66位块边界的“寻线”模式。

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