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1. 发明授权

US09157950B2 Loop parameter sensor using repetitive phase errors 有权
标题翻译：循环参数传感器使用重复相位误差
公开(公告)号：US09157950B2
公开(公告)日：2015-10-13
申请号：US13088949
申请日：2011-04-18
申请人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
发明人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
IPC分类号： G01R25/00 , G01R31/28 , H03L7/093 , H03L7/107 , H03L7/18
CPC分类号： H03L7/085 , G01R31/2824 , H03L7/093 , H03L7/1075 , H03L7/1077 , H03L7/18 , H03L2207/06
摘要： A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.
摘要翻译：公开了用于测量锁相环频率合成器（PLL）中的指定参数的方法和系统。在一个实施例中，该方法包括在PLL中引入多个相位误差，测量所引入的相位误差的特定方面，以及使用引入的相位误差的测量方面来确定所述指定参数的值。在一个实施例中，在PLL中重复地引入相位误差，并且这些相位误差在PPL中产生参考信号和反馈信号之间的修正的相位差。在一个实施例中，当修改的相位差超过预设值时，交叉时间被确定，并且这些交叉时间被用于确定指定参数的值。在一个实施例中，该参数被计算为交叉时间的数学函数。该参数可以是例如PLL的带宽。

2. 发明申请

US20120262149A1 LOOP PARAMETER SENSOR USING REPETITIVE PHASE ERRORS 有权
标题翻译：使用重复相位错误的环路参数传感器
公开(公告)号：US20120262149A1
公开(公告)日：2012-10-18
申请号：US13088949
申请日：2011-04-18
申请人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
发明人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
IPC分类号： G01R25/00
CPC分类号： H03L7/085 , G01R31/2824 , H03L7/093 , H03L7/1075 , H03L7/1077 , H03L7/18 , H03L2207/06
摘要： A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.
摘要翻译：公开了用于测量锁相环频率合成器（PLL）中的指定参数的方法和系统。在一个实施例中，该方法包括在PLL中引入多个相位误差，测量所引入的相位误差的特定方面，以及使用引入的相位误差的测量方面来确定所述指定参数的值。在一个实施例中，在PLL中重复地引入相位误差，并且这些相位误差在PPL中产生参考信号和反馈信号之间的修正的相位差。在一个实施例中，当修改的相位差超过预设值时，交叉时间被确定，并且这些交叉时间被用于确定指定参数的值。在一个实施例中，该参数被计算为交叉时间的数学函数。该参数可以是例如PLL的带宽。

3. 发明授权

US07602869B2 Methods and apparatus for clock synchronization and data recovery in a receiver 有权
标题翻译：接收机中时钟同步和数据恢复的方法和装置
公开(公告)号：US07602869B2
公开(公告)日：2009-10-13
申请号：US11193868
申请日：2005-07-29
申请人： Azita Emami-Neyestanak , Mounir Meghelli , Benjamin D. Parker , Sergey V. Rylov , Alexander V. Rylyakov , Jose A. Tierno
发明人： Azita Emami-Neyestanak , Mounir Meghelli , Benjamin D. Parker , Sergey V. Rylov , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point. Further, for a next sampling cycle, the first clock may be used to sweep through phase positions with respect to the set phase position of the second clock corresponding to the sampling point in the first sampling cycle such that a next sampling point may be determined.
摘要翻译：公开了时钟同步和数据恢复技术。例如，用于同步用于恢复接收到的数据的时钟的技术包括以下步骤/操作。将第一时钟（例如，数据时钟）设置为在接收到的数据中的给定单位间隔内的第一相位位置的第一采样周期。第二时钟（例如，扫描时钟）相对于第一相位位置扫过其它相位位置，从而确定从接收到的数据中的给定单位间隔到另一个单位间隔的转变。基于与第二时钟相关联的相位位置处的测量来确定采样点。将第二时钟设置为对应于采样点的相位位置，使得可以在该采样点恢复数据。此外，对于下一采样周期，可以使用第一时钟相对于与第一采样周期中的采样点对应的第二时钟的设置相位位置扫描相位位置，使得可以确定下一采样点。

4. 发明授权

US08570079B2 Reducing phase locked loop phase lock time 有权
标题翻译：减少锁相环锁相时间
公开(公告)号：US08570079B2
公开(公告)日：2013-10-29
申请号：US13226557
申请日：2011-09-07
申请人： Mark Ferriss , Alexander V. Rylyakov , Jose A. Tierno
发明人： Mark Ferriss , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L2207/06
摘要： There is provided a method for reducing lock time in a phase locked loop. The method includes detecting a saturation condition on a path within the phase locked loop. The method further includes temporarily applying saturation compensation along the path when the saturation condition is detected.
摘要翻译：提供了一种减少锁相环锁定时间的方法。该方法包括检测锁相环内的路径上的饱和状态。该方法还包括当检测到饱和条件时，沿路径暂时施加饱和补偿。

5. 发明申请

US20130076449A1 VARACTOR TUNING CONTROL USING REDUNDANT NUMBERING 失效
标题翻译：使用冗余编号的变频调速控制
公开(公告)号：US20130076449A1
公开(公告)日：2013-03-28
申请号：US13245409
申请日：2011-09-26
申请人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L2207/50
摘要： Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tunings steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering.
摘要翻译：公开了用于改进变容二极管电路调谐控制的技术。例如，一种装置包括用于调谐频率值的多个变容二极管。多个变容二极管包括大约sqrt（2N）变容二极管，其中N是调谐步骤的数量，并且多个变容二极管分别尺寸为1x，2x，3x，4x。。。，约为sqrt（2N）x，其中x为电容单位。 N个调谐步骤中的给定一个可以由多个组合的变容二极管表示。这可以称为冗余编号。

6. 发明授权

US08264285B2 Method and apparatus for low latency proportional path in a digitally controlled system 有权
标题翻译：数字控制系统中低延迟比例路径的方法和装置
公开(公告)号：US08264285B2
公开(公告)日：2012-09-11
申请号：US12175012
申请日：2008-07-17
申请人： Alexander V. Rylyakov , Jose A. Tierno
发明人： Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/093 , H03L7/099 , H03L2207/06
摘要： A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).
摘要翻译：数字控制电路和方法包括耦合到比例路径的误差输入。比例路径包括直接接收误差输入作为选择信号的选择器。选择器从比例路径（其中比例控制权重被输入到数字控制振荡器（DCO））以外的位置接收比例控制权重。

7. 发明授权

US07772900B2 Phase-locked loop circuits and methods implementing pulsewidth modulation for fine tuning control of digitally controlled oscillators 失效
标题翻译：锁相环电路和实现脉冲宽度调制的方法，用于数字控制振荡器的微调控制
公开(公告)号：US07772900B2
公开(公告)日：2010-08-10
申请号：US12173140
申请日：2008-07-15
申请人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/107 , H03L7/093 , H03L7/1075 , H03L2207/50
摘要： PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to further modulate dithered control signals that are used to enhance the frequency tuning resolution of the DCO such that the dithered control signals are applied to the fractional tracking control port of the DCO for a selected fraction of a full clock signal based pulse width modulation applied.
摘要翻译：提供PLL（锁相环）电路和方法，其中PWM（脉宽调制）技术将实现DCO（数字控制振荡器）电路的连续微调控制。通常，应用脉冲宽度调制技术来进一步调制用于增强DCO的频率调谐分辨率的抖动控制信号，使得抖动控制信号被施加到DCO的分数跟踪控制端口，用于所选择的部分采用全时钟信号脉冲宽度调制。

8. 发明申请

US20090195278A1 METHOD AND CIRCUIT FOR CONTROLLING CLOCK FREQUENCY OF AN ELECTRONIC CIRCUIT WITH NOISE MITIGATION 有权
标题翻译：用于控制具有噪声减轻的电子电路的时钟频率的方法和电路
公开(公告)号：US20090195278A1
公开(公告)日：2009-08-06
申请号：US12023933
申请日：2008-01-31
申请人： Daniel Joseph Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Daniel Joseph Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/06 , H03D3/26
CPC分类号： H03L7/1976 , H03L2207/50
摘要： A technique to mitigate noise spikes in an electronic circuit device such as an integrated circuit. The clock frequency of a clock signal used by the electronic circuit is controlled such that instantaneously large changes to the clock frequency are avoided by use of a frequency filter that is capable of generating frequency ramps having a linear slope which is used as a feedback signal in a digital phase-locked loop clock circuit in lieu of a discrete, stair-stepped feedback control signal.
摘要翻译：一种减轻诸如集成电路的电子电路装置中的噪声尖峰的技术。控制由电子电路使用的时钟信号的时钟频率，使得能够通过使用能够产生具有用作反馈信号的线性斜率的频率斜坡的频率滤波器来避免对时钟频率的瞬时大的改变数字锁相环时钟电路代替离散的楼梯阶反馈控制信号。

9. 发明授权

US07443251B2 Digital phase and frequency detector 失效
标题翻译：数字相位和频率检测器
公开(公告)号：US07443251B2
公开(公告)日：2008-10-28
申请号：US11610900
申请日：2006-12-14
申请人： Alexander V. Rylyakov , Jose A. Tierno
发明人： Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/085
CPC分类号： H03L7/091 , H03L7/093 , H03L2207/50
摘要： Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.
摘要翻译：公开了一种数字相位频率检测器和操作数字相位频率检测器的方法。检测器包括输入电路，输出电路和复位电路。在使用中，输入电路在多个周期期间接收第一和第二输入信号，并且在给定的一个周期期间，根据第一和第二输入信号中的哪一个首先被接收来产生第一中间信号或第二中间信号在给定一个所述周期期间。输出电路接收这些中间信号，并且在所述一个周期期间输出第一输出信号或第二输出信号，取决于在所述一个周期期间由输出电路接收到哪个中间信号。复位电路在限定的条件下向输入电路施加复位信号以开始所述多个周期中的新的周期。

10. 发明授权

US08704567B2 Hybrid phase-locked loop architectures 有权
公开(公告)号：US08704567B2
公开(公告)日：2014-04-22
申请号：US13611008
申请日：2012-09-12
申请人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Mark A. Ferriss , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/1072 , H03L7/087 , H03L7/089 , H03L7/093
摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

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