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1. 发明授权

US5021353A Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions 失效
标题翻译：分离多晶硅CMOS工艺结合导电区域的自对准硅化物
公开(公告)号：US5021353A
公开(公告)日：1991-06-04
申请号：US485029
申请日：1990-02-26
申请人： Tyler A. Lowrey , Dermot M. Durcan , Trung T. Doan , Gordon A. Haller , Mark E. Tuttle
发明人： Tyler A. Lowrey , Dermot M. Durcan , Trung T. Doan , Gordon A. Haller , Mark E. Tuttle
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/665 , H01L21/823835
摘要： An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly) and incorporates self-aligned salicidation of conductive regions. The object of the improved process is to reduce the cost and improve the reliability, performance and manufacturability of CMOS devices by a process which features a dramatically reduced number of photomasking steps and which further allows self-aligned salicidation of transistor conductive regions. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology: Use of a masked high-energy punch-through implant for N-channel devices is not required; individual optimization of N-channel and P-channel transistors is made possible; a lightly-doped drain (LDD) design for both N-channel and P-channel transistors is readily implemented; source/drain-to-gate offset may be changed independently for N-channel and P-channel devices; and N-channel and P-channel transistors can be independently controlled and optimized for best LDD performance and reliability.
摘要翻译：一种改进的CMOS制造工艺，其使用单独的掩模步骤来从单层导电掺杂多晶硅（poly）中的N沟道和P沟道晶体管栅极图案化，并且引入导电区域的自对准的阳离子化。改进方法的目的是降低成本，并且通过具有显着减少的光掩模步骤数目并进一步允许晶体管导电区域的自对准盐化的方法来降低CMOS器件的可靠性，性能和可制造性。通过分别处理N沟道和P沟道器件，在单多晶硅层或单金属层工艺中制造完整的CMOS电路所需的光掩模步骤的数量可以从11减少到8个。从P型材料的衬底开始，首先形成N沟道器件，在未来的P沟道区域中留下未蚀刻的聚合物，直到N沟道处理完成。与传统工艺技术相比，改进的CMOS工艺提供了以下优点：不需要对N沟道器件使用掩模的高能穿孔注入器; N通道和P沟道晶体管的单独优化成为可能; 容易实现用于N沟道和P沟道晶体管的轻掺杂漏极（LDD）设计; 源/漏 - 门偏移可以针对N沟道和P沟道器件独立地改变; 可以独立控制和优化N沟道和P沟道晶体管，以获得最佳的LDD性能和可靠性。

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