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1. 发明授权

US5021353A Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions 失效
标题翻译：分离多晶硅CMOS工艺结合导电区域的自对准硅化物
公开(公告)号：US5021353A
公开(公告)日：1991-06-04
申请号：US485029
申请日：1990-02-26
申请人： Tyler A. Lowrey , Dermot M. Durcan , Trung T. Doan , Gordon A. Haller , Mark E. Tuttle
发明人： Tyler A. Lowrey , Dermot M. Durcan , Trung T. Doan , Gordon A. Haller , Mark E. Tuttle
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/665 , H01L21/823835
摘要： An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly) and incorporates self-aligned salicidation of conductive regions. The object of the improved process is to reduce the cost and improve the reliability, performance and manufacturability of CMOS devices by a process which features a dramatically reduced number of photomasking steps and which further allows self-aligned salicidation of transistor conductive regions. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology: Use of a masked high-energy punch-through implant for N-channel devices is not required; individual optimization of N-channel and P-channel transistors is made possible; a lightly-doped drain (LDD) design for both N-channel and P-channel transistors is readily implemented; source/drain-to-gate offset may be changed independently for N-channel and P-channel devices; and N-channel and P-channel transistors can be independently controlled and optimized for best LDD performance and reliability.
摘要翻译：一种改进的CMOS制造工艺，其使用单独的掩模步骤来从单层导电掺杂多晶硅（poly）中的N沟道和P沟道晶体管栅极图案化，并且引入导电区域的自对准的阳离子化。改进方法的目的是降低成本，并且通过具有显着减少的光掩模步骤数目并进一步允许晶体管导电区域的自对准盐化的方法来降低CMOS器件的可靠性，性能和可制造性。通过分别处理N沟道和P沟道器件，在单多晶硅层或单金属层工艺中制造完整的CMOS电路所需的光掩模步骤的数量可以从11减少到8个。从P型材料的衬底开始，首先形成N沟道器件，在未来的P沟道区域中留下未蚀刻的聚合物，直到N沟道处理完成。与传统工艺技术相比，改进的CMOS工艺提供了以下优点：不需要对N沟道器件使用掩模的高能穿孔注入器; N通道和P沟道晶体管的单独优化成为可能; 容易实现用于N沟道和P沟道晶体管的轻掺杂漏极（LDD）设计; 源/漏 - 门偏移可以针对N沟道和P沟道器件独立地改变; 可以独立控制和优化N沟道和P沟道晶体管，以获得最佳的LDD性能和可靠性。

2. 发明授权

US07009298B2 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer 失效
标题翻译：具有硅化钛界面的硅的低电阻接触和无定形氮化钛氮化硼阻挡层
公开(公告)号：US07009298B2
公开(公告)日：2006-03-07
申请号：US10639120
申请日：2003-08-11
申请人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
发明人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
IPC分类号： H01L21/302
CPC分类号： H01L21/76855 , C23C16/34 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76862
摘要： A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor.
摘要翻译：提供了一种接触结构，其结合使用四 - 二烷基酰氨基 - 钛，Ti（NMe 2 O 3）4 Si 3 O 4的低压化学气相沉积（LPCVD）形成的无定形氮化钛阻挡层。，作为前体。

3. 发明授权

US5372973A Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology 失效
标题翻译：使用化学机械抛光技术在冷阴极发射器尖端周围形成自对准栅极结构的方法
公开(公告)号：US5372973A
公开(公告)日：1994-12-13
申请号：US53794
申请日：1993-04-27
申请人： Trung T. Doan , J. Brett Rolfson , Tyler A. Lowrey , David A. Cathey
发明人： Trung T. Doan , J. Brett Rolfson , Tyler A. Lowrey , David A. Cathey
IPC分类号： H01J1/304 , H01J9/02 , H01L21/3105 , H01L21/465
CPC分类号： H01J9/025 , H01L21/31053 , H01J2201/30426 , H01J2201/319 , H01J2209/0226
摘要： A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.
摘要翻译：用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极结构的化学机械抛光工艺，其中发射尖端i）可选地通过氧化锐化，ii）用保形绝缘材料沉积，iii）沉积具有可流动的绝缘材料，其被回流到尖端的水平面以下，iv）任选地沉积有另外的绝缘材料，v）沉积有导电材料层，以及vi）任选地沉积有缓冲材料，vii）化学机械平面化（CMP）步骤，暴露保形绝缘层，viii）湿式蚀刻以去除绝缘材料，从而暴露发射尖端，之后ix）发射极尖端可以涂覆具有比硅功函数低的材料。

4. 发明授权

US5229331A Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology 失效
标题翻译：使用化学机械抛光技术在冷阴极发射器尖端周围形成自对准栅极结构的方法
公开(公告)号：US5229331A
公开(公告)日：1993-07-20
申请号：US837453
申请日：1992-02-14
申请人： Trung T. Doan , J. Brett Rolfson , Tyler A. Lowrey , David A. Cathey
发明人： Trung T. Doan , J. Brett Rolfson , Tyler A. Lowrey , David A. Cathey
IPC分类号： H01J1/304 , H01J9/02 , H01L21/3105
CPC分类号： H01J9/025 , H01L21/31053 , H01J2201/30426 , H01J2201/319 , H01J2209/0226
摘要： A chemical mechanical polishing process for the formation of self-aligned gate structures surrounding an electron emission tip for use in field emission displays in which the emission tip is i) optionally sharpened through oxidation, ii) deposited with a conformal insulating material, iii) deposited with a flowable insulating material, which is reflowed below the level of the tip, iv) optionally deposited with another insulating material, v) deposited with a conductive material layer, and vi) optionally, deposited with a buffering material, vii) planarized with a chemical mechanical planarization (CMP) step, to expose the conformal insulating layer, viii) wet etched to remove the insulating material and thereby expose the emission tip, afterwhich ix) the emitter tip may be coated with a material having a lower work function than silicon.
摘要翻译：用于形成围绕用于场发射显示器中的电子发射尖端的自对准栅极结构的化学机械抛光工艺，其中发射尖端i）可选地通过氧化锐化，ii）用保形绝缘材料沉积，iii）沉积具有可流动的绝缘材料，其被回流到尖端的水平面以下，iv）任选地沉积有另外的绝缘材料，v）沉积有导电材料层，以及vi）任选地沉积有缓冲材料，vii）化学机械平面化（CMP）步骤，暴露保形绝缘层，viii）湿式蚀刻以去除绝缘材料，从而暴露发射尖端，之后ix）发射极尖端可以涂覆具有比硅功函数低的材料。

5. 发明授权

US06903010B2 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer 失效
标题翻译：具有硅化钛界面的硅的低电阻接触和无定形氮化钛氮化硼阻挡层
公开(公告)号：US06903010B2
公开(公告)日：2005-06-07
申请号：US10637427
申请日：2003-08-08
申请人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
发明人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
IPC分类号： C23C16/34 , H01L21/285 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76855 , C23C16/34 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76862
摘要： A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through a dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon or of a metal follows.
摘要翻译：提供了一种接触结构，其结合使用四 - 二烷基酰氨基 - 钛，Ti（NMe 2 O 3）4 Si 3 O 4的低压化学气相沉积（LPCVD）形成的无定形氮化钛阻挡层。，作为前体。通过将通过电介质层的接触开口蚀刻到要进行电接触的扩散区域来制造接触结构。钛金属沉积在晶片的表面上，使得扩散区域的暴露表面完全被金属层覆盖。钛金属层的至少一部分最终被转化为硅化钛，从而在扩散区的表面提供优异的导电界面。然后使用LPCVD工艺沉积氮化钛阻挡层，涂覆接触开口的壁和底板。以下是多晶硅或金属的化学气相沉积。

6. 发明授权

US06632736B2 Method of forming low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer 失效
标题翻译：与具有钛硅化物界面的硅形成低电阻接触的方法和无定形氮化钛氮化硼阻挡层
公开(公告)号：US06632736B2
公开(公告)日：2003-10-14
申请号：US09921615
申请日：2001-08-03
申请人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
发明人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
IPC分类号： H01L214763
CPC分类号： H01L21/76855 , C23C16/34 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76862
摘要： A contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon or of a metal follows.
摘要翻译： Ti（NMe PDAT> 2 ）通过低压化学气相沉积（LPCVD）形成的非晶氮化钛阻挡层的接触结构， PDAT> 4 作为前体。通过将通过电介质层的接触开口蚀刻到要进行电接触的扩散区域来制造接触结构。钛金属沉积在晶片的表面上，使得扩散区域的暴露表面完全被金属层覆盖。钛金属层的至少一部分最终被转化为硅化钛，从而在扩散区的表面提供优异的导电界面。然后使用LPCVD工艺沉积氮化钛阻挡层，涂覆接触开口的壁和底板。多晶硅或金属的化学气相沉积如下

7. 发明授权

US5723382A Method of making a low-resistance contact to silicon having a titanium silicide interface, an amorphous titanium nitride barrier layer and a conductive plug 失效
标题翻译：对具有钛硅化物界面的硅进行低电阻接触的方法，非晶氮化钛阻挡层和导电插塞
公开(公告)号：US5723382A
公开(公告)日：1998-03-03
申请号：US509708
申请日：1995-07-31
申请人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
发明人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
IPC分类号： C23C16/34 , H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76855 , C23C16/34 , H01L21/28568 , H01L21/76843
摘要： This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon, or of metal, such as tungsten, follows, and proceeds until the contact opening is completely filled with either polycrystalline silicon or metal.
摘要翻译：本发明构成了采用利用四 - 二烷基酰胺基钛，Ti（NMe 2）4作为前体的低压化学气相沉积（LPCVD）形成的无定形氮化钛阻挡层的接触结构。通过将通过电介质层的接触开口蚀刻到要进行电接触的扩散区域来制造接触结构。钛金属沉积在晶片的表面上，使得扩散区域的暴露表面完全被金属层覆盖。钛金属层的至少一部分最终被转化为硅化钛，从而在扩散区的表面提供优异的导电界面。然后使用LPCVD工艺沉积氮化钛阻挡层，涂覆接触开口的壁和底板。多晶硅或金属如钨的化学气相沉积随后进行，直到接触开口完全充满多晶硅或金属。

8. 发明授权

US06624517B1 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer 失效
标题翻译：具有硅化钛界面的硅的低电阻接触和无定形氮化钛氮化硼阻挡层
公开(公告)号：US06624517B1
公开(公告)日：2003-09-23
申请号：US09505213
申请日：2000-02-16
申请人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
发明人： Gurtej S. Sandhu , Trung T. Doan , Tyler A. Lowrey
IPC分类号： H01L2348
CPC分类号： H01L21/76855 , C23C16/34 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76862
摘要： This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon, or of metal, such as tungsten, follows, and proceeds until the contact opening is completely filled with either polycrystalline silicon or metal.
摘要翻译：本发明构成了采用利用四 - 二烷基酰胺基钛，Ti（NMe 2）4作为前体的低压化学气相沉积（LPCVD）形成的非晶氮化钛阻挡层的接触结构。通过将通过电介质层的接触开口蚀刻到要进行电接触的扩散区域来制造接触结构。钛金属沉积在晶片的表面上，使得扩散区域的暴露表面完全被金属层覆盖。钛金属层的至少一部分最终被转化为硅化钛，从而在扩散区的表面提供优异的导电界面。然后使用LPCVD工艺沉积氮化钛阻挡层，涂覆接触开口的壁和底板。多晶硅或金属如钨的化学气相沉积随后进行，直到接触开口完全充满多晶硅或金属。

9. 发明授权

US5653619A Method to form self-aligned gate structures and focus rings 失效
标题翻译：形成自对准栅极结构和聚焦环的方法
公开(公告)号：US5653619A
公开(公告)日：1997-08-05
申请号：US300985
申请日：1994-09-06
申请人： Eugene H. Cloud , Trung T. Doan , Tyler A. Lowrey , David A. Cathey , J. Brett Rolfson
发明人： Eugene H. Cloud , Trung T. Doan , Tyler A. Lowrey , David A. Cathey , J. Brett Rolfson
IPC分类号： H01J9/02 , H01J1/30
CPC分类号： H01J9/025 , H01J2209/0226 , H01J2329/00
摘要： A selective etching and chemical mechanical planarization process is employed for the formation of self-aligned gate and focus ring structures surrounding an electron emission tip for use in field emission displays. The process is employed to construct an emission grid whereby the gate structure is capable of producing a field strength at the cathode tip sufficient to generate electron emission. The gate is disposed at a location above the tip such that the gate physically intercepts the outermost lateral portions of the beam, yet does not induce a significant electrostatic outward divergence of the beam, thereby reducing the cross-section of the beam.
摘要翻译：采用选择性蚀刻和化学机械平面化方法来形成围绕用于场发射显示器的电子发射尖端的自对准栅极和聚焦环结构。该方法用于构建发射栅极，由此栅极结构能够在阴极尖端产生足以产生电子发射的场强。门设置在尖端上方的位置，使得栅极物理地截取梁的最外侧部分，但不会引起梁的显着的静电向外发散，从而减小梁的横截面。

10. 发明授权

US5438240A Field emission structures produced on macro-grain polysilicon substrates 失效
标题翻译：在大颗粒多晶硅基板上产生的场致发射结构
公开(公告)号：US5438240A
公开(公告)日：1995-08-01
申请号：US232792
申请日：1994-04-22
申请人： David A. Cathey , J. Brett Rolfson , Tyler A. Lowrey , Trung T. Doan
发明人： David A. Cathey , J. Brett Rolfson , Tyler A. Lowrey , Trung T. Doan
IPC分类号： H01J1/30 , H01J1/304 , H01J9/02 , H01J29/04 , H01J31/12
CPC分类号： H01J1/3042 , H01J9/025 , H01J2201/30407
摘要： A baseplate for a flat panel display comprising relatively thick semiconductor substrate, wherein the semiconductor substrate is a macro-grain polycrystalline substrate, which is amorphized by ion implantation or reformed by recrystallization, to obscure the grain boundaries, thereafter redundant circuitry may be fabricated thereon to further enhance product yield.
摘要翻译：一种用于平板显示器的底板，包括相对厚的半导体衬底，其中半导体衬底是通过离子注入而非晶化或通过重结晶重新形成的宏晶多晶衬底，以掩盖晶界，此后可制造冗余电路，进一步提高产品产量。

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