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1. 发明申请

US20050158992A1 Cladded conductor for use in a magnetoelectronics device and method for fabricating the same 失效
公开(公告)号：US20050158992A1
公开(公告)日：2005-07-21
申请号：US11082617
申请日：2005-03-16
申请人： Mark Durlam , Jeffrey Baker , Brian Butcher , Mark Deherrera , John D'Urso , Earl Fuchs , Gregory Grynkewich , Kelly Kyler , Jaynal Molla , J. Ren , Nicholas Rizzo
发明人： Mark Durlam , Jeffrey Baker , Brian Butcher , Mark Deherrera , John D'Urso , Earl Fuchs , Gregory Grynkewich , Kelly Kyler , Jaynal Molla , J. Ren , Nicholas Rizzo
IPC分类号： G11C11/15 , H01L21/02 , H01L27/22 , H01L43/12 , H01L21/44 , H01L21/00
CPC分类号： H01L27/222 , G11C11/15 , H01L28/10 , H01L43/12
摘要： A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).

2. 发明申请

US20050164413A1 METHOD FOR FABRICATING A FLUX CONCENTRATING SYSTEM FOR USE IN A MAGNETOELECTRONICS DEVICE 有权
标题翻译：一种用于磁电子设备的通量浓度系统的制造方法
公开(公告)号：US20050164413A1
公开(公告)日：2005-07-28
申请号：US10324716
申请日：2002-12-19
申请人： Thomas Meixner , Gregory Grynkewich , Jaynal Molla , J. Ren , Richard Williams , Brian Butcher , Mark Durlam
发明人： Thomas Meixner , Gregory Grynkewich , Jaynal Molla , J. Ren , Richard Williams , Brian Butcher , Mark Durlam
IPC分类号： G11C11/16 , H01L21/8246 , H01L21/00 , H01L21/20
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/16 , H01L43/12
摘要： A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
摘要翻译：提供了一种用于制造用于磁电装置的通量集中系统（62）的方法。该方法包括以下步骤：提供在衬底（12）中形成的位线（10），并形成覆盖位线（10）和衬底（12）的第一材料层（24）。进行蚀刻以在第一材料层（24）中形成沟槽（58），并且在沟槽（52）中沉积包层（56）。缓冲材料层（58）形成在覆层（56）上，缓冲材料层（58）的一部分和包覆层（56）的一部分被去除。

3. 发明申请

US20050208681A1 Method for fabricating a flux concentrating system for use in a magnetoelectronics device 失效
公开(公告)号：US20050208681A1
公开(公告)日：2005-09-22
申请号：US11125955
申请日：2005-05-09
申请人： Thomas Meixner , Gregory Grynkewich , Jaynal Molla , J. Ren , Richard Williams , Brian Butcher , Mark Durlam
发明人： Thomas Meixner , Gregory Grynkewich , Jaynal Molla , J. Ren , Richard Williams , Brian Butcher , Mark Durlam
IPC分类号： G11C11/16 , H01L21/8246 , H01L21/8239 , H01L21/44
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/16 , H01L43/12
摘要： A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.

4. 发明申请

US20050130374A1 Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices 有权
公开(公告)号：US20050130374A1
公开(公告)日：2005-06-16
申请号：US11050191
申请日：2005-02-02
申请人： Gregory Grynkewich , Brian Butcher , Mark Durlam , Kelly Kyler , Charles Synder , Kenneth Smith , Clarence Tracy , Richard Williams
发明人： Gregory Grynkewich , Brian Butcher , Mark Durlam , Kelly Kyler , Charles Synder , Kenneth Smith , Clarence Tracy , Richard Williams
IPC分类号： G11C11/15 , H01L21/8246 , H01L43/12 , H01L21/336
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/15 , H01L43/12
摘要： A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

5. 发明申请

US20060170068A1 MAGNETOELECTRONIC DEVICES UTILIZING PROTECTIVE CAPPING LAYERS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：使用保护层的磁电装置及其制造方法
公开(公告)号：US20060170068A1
公开(公告)日：2006-08-03
申请号：US11048015
申请日：2005-01-31
申请人： J. Ren , Brian Butcher , Mark Durlam , Gregory Grynkewich
发明人： J. Ren , Brian Butcher , Mark Durlam , Gregory Grynkewich
IPC分类号： H01L43/00 , H01L29/82
CPC分类号： H01L43/12 , H01L27/228
摘要： Magnetoelectronic device structures and methods for fabricating the same are provided. One method comprises forming a first and a second conductor. The first conductor is electrically coupled to an interconnect stack. A first insulating layer is deposited overlying the first conductor and the second conductor. A via is etched to substantially expose the first conductor. A protective capping layer is deposited by electroless deposition within the via and is electrically coupled to the first conductor. A magnetic memory element layer is formed within the via and overlying the second insulating layer and the second conductor.
摘要翻译：提供了磁电子器件结构及其制造方法。一种方法包括形成第一和第二导体。第一导体电耦合到互连叠层。沉积在第一导体和第二导体上的第一绝缘层。蚀刻通孔以基本上暴露第一导体。通过无孔沉积在通孔内沉积保护性覆盖层并电耦合到第一导体。磁通存储元件层形成在通孔内并覆盖第二绝缘层和第二导体。

6. 发明申请

US20050009212A1 Magnetoresistive random access memory devices and methods for fabricating the same 有权
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US20050009212A1
公开(公告)日：2005-01-13
申请号：US10912979
申请日：2004-08-05
申请人： Gregory Grynkewich , Brian Butcher , Mark Durlam , Clarence Tracy
发明人： Gregory Grynkewich , Brian Butcher , Mark Durlam , Clarence Tracy
IPC分类号： G11C11/16 , H01L21/00 , H01L21/8246 , H01L27/22 , H01L29/76
CPC分类号： G11C11/16 , B82Y10/00 , H01L27/228
摘要： Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.
摘要翻译：制造磁阻随机存取存储器单元和用于磁阻随机存取存储单元的结构开始于提供其中形成有晶体管的衬底。形成电耦合到晶体管的接触元件，并且电介质材料沉积在由接触元件部分界定的区域内。在电介质材料内形成数字线，数字线覆盖接触元件的一部分。导电层形成在数字线上方并与接触元件电连通。

7. 发明申请

US20070045759A1 Passive elements in MRAM embedded integrated circuits 有权
公开(公告)号：US20070045759A1
公开(公告)日：2007-03-01
申请号：US11217146
申请日：2005-08-31
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
IPC分类号： H01L43/00
CPC分类号： H01L27/228
摘要： An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

8. 发明申请

US20070002609A1 MRAM embedded smart power integrated circuits 有权
标题翻译： MRAM嵌入式智能电源集成电路
公开(公告)号：US20070002609A1
公开(公告)日：2007-01-04
申请号：US11170874
申请日：2005-06-30
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric Salter
IPC分类号： G11C11/14
CPC分类号： G11C11/1659 , H01F10/3254
摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
摘要翻译：集成电路装置包括使用相同的制造工艺技术在同一衬底上形成的磁性随机存取存储器（“MRAM”）架构和智能电力集成电路架构。制造工艺技术是具有前端工艺和后端工艺的模块化工艺。在该示例性实施例中，智能功率架构包括由前端处理形成的电源电路部件，数字逻辑部件和模拟控制部件以及由后端处理形成的传感器架构。 MRAM架构包括由前端处理形成的MRAM电路部件和由后端处理形成的MRAM单元阵列。在一个实际实施例中，传感器架构包括由MRAM单元阵列使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

9. 发明申请

US20070097732A1 MAGNETIC TUNNEL JUNCTION CURRENT SENSORS 有权
公开(公告)号：US20070097732A1
公开(公告)日：2007-05-03
申请号：US11262053
申请日：2005-10-28
申请人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric salter , Jiang-Kai Zuo
发明人： Young Chung , Robert Baird , Mark Durlam , Gregory Grynkewich , Eric salter , Jiang-Kai Zuo
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673
摘要： An integrated circuit device is provided which includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit component. The current sensor may comprise a Magnetic Tunnel Junction (“MTJ”) core disposed between the first conductive layer and the second conductive layer. The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.
摘要翻译：提供一种集成电路装置，其包括有源电路部件和电流传感器。有源电路组件可以耦合在第一导电层和第二导电层之间，并且被配置为产生第一电流。电流传感器设置在有源电路部件上。电流传感器可以包括设置在第一导电层和第二导电层之间的磁隧道结（“MTJ”）芯。 MTJ内核被配置为基于在MTJ核心处感测到的第一电流来感测第一电流并产生第二电流。

10. 发明授权

US06331943B1 MTJ MRAM series-parallel architecture 失效
标题翻译： MTJ MRAM系列并行架构
公开(公告)号：US06331943B1
公开(公告)日：2001-12-18
申请号：US09649117
申请日：2000-08-28
申请人： Peter K. Naji , Mark DeHerrera , Mark Durlam
发明人： Peter K. Naji , Mark DeHerrera , Mark Durlam
IPC分类号： G11C1100
CPC分类号： H01L27/228 , G11C11/15
摘要： Magnetic tunnel junction random access memory architecture in which an array of memory cells is arranged in rows and columns and each memory cell includes a magnetic tunnel junction and a control transistor connected in parallel. A control line is connected to the gate of each control transistor in a row of control transistors and a metal programming line extending adjacent to each magnetic tunnel junction is connected to the control line in spaced apart intervals by vias. Further, groups of memory cells in each column are connected in series to form local bit lines which are connected in parallel to global bit lines. The series-parallel configuration is read using a centrally located column to provide a reference signal and data from columns on each side of the reference column is compared to the reference signal or two columns in proximity are differentially compared.
摘要翻译：磁性隧道结随机存取存储器结构，其中存储器单元阵列以行和列排列，并且每个存储单元包括并行连接的磁性隧道结和控制晶体管。控制线连接到一排控制晶体管中的每个控制晶体管的栅极，并且与每个磁性隧道结相邻的金属编程线通过通孔以间隔开的间隔连接到控制线。此外，每列中的存储单元组被串联连接以形成与全局位线并行连接的局部位线。使用位于中心的列来读取串并联配置以提供参考信号，并且将参考列的每一侧的列中的数据与参考信号进行比较或差异地比较两个接近的列。

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