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1. 发明申请

US20050130374A1 Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices 有权
公开(公告)号：US20050130374A1
公开(公告)日：2005-06-16
申请号：US11050191
申请日：2005-02-02
申请人： Gregory Grynkewich , Brian Butcher , Mark Durlam , Kelly Kyler , Charles Synder , Kenneth Smith , Clarence Tracy , Richard Williams
发明人： Gregory Grynkewich , Brian Butcher , Mark Durlam , Kelly Kyler , Charles Synder , Kenneth Smith , Clarence Tracy , Richard Williams
IPC分类号： G11C11/15 , H01L21/8246 , H01L43/12 , H01L21/336
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/15 , H01L43/12
摘要： A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

2. 发明申请

US20050009212A1 Magnetoresistive random access memory devices and methods for fabricating the same 有权
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US20050009212A1
公开(公告)日：2005-01-13
申请号：US10912979
申请日：2004-08-05
申请人： Gregory Grynkewich , Brian Butcher , Mark Durlam , Clarence Tracy
发明人： Gregory Grynkewich , Brian Butcher , Mark Durlam , Clarence Tracy
IPC分类号： G11C11/16 , H01L21/00 , H01L21/8246 , H01L27/22 , H01L29/76
CPC分类号： G11C11/16 , B82Y10/00 , H01L27/228
摘要： Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.
摘要翻译：制造磁阻随机存取存储器单元和用于磁阻随机存取存储单元的结构开始于提供其中形成有晶体管的衬底。形成电耦合到晶体管的接触元件，并且电介质材料沉积在由接触元件部分界定的区域内。在电介质材料内形成数字线，数字线覆盖接触元件的一部分。导电层形成在数字线上方并与接触元件电连通。

3. 发明申请

US20050020053A1 Method and structure for contacting an overlying electrode for a magnetoelectronics element 失效
标题翻译：用于接触磁电元件的上覆电极的方法和结构
公开(公告)号：US20050020053A1
公开(公告)日：2005-01-27
申请号：US10922436
申请日：2004-08-19
申请人： Brian Butcher , Kenneth Smith , Clarence Tracy
发明人： Brian Butcher , Kenneth Smith , Clarence Tracy
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/22 , H01L29/94 , H01L43/12
CPC分类号： H01L27/222 , H01L43/12
摘要： A method for contacting an electrically conductive electrode overlying a first dielectric material of a structure is provided. The method includes forming a mask layer overlying the electrically conductive electrode and patterning the mask layer to form an exposed electrically conductive electrode material. At least a portion of the exposed electrically conductive electrode material is removed while an electrically conductive veil is formed adjacent the mask layer. A metal contact layer is formed such that said metal contact layer contacts the electrically conductive veil.
摘要翻译：提供了一种用于接触覆盖结构的第一介电材料的导电电极的方法。该方法包括形成覆盖在导电电极上的掩模层并且图案化掩模层以形成暴露的导电电极材料。暴露的导电电极材料的至少一部分被去除，同时在掩模层附近形成导电面纱。形成金属接触层，使得所述金属接触层接触导电面纱。

4. 发明申请

US20070054474A1 Crack-free III-V epitaxy on germanium on insulator (GOI) substrates 审中-公开
标题翻译：锗绝缘体（GOI）衬底上无裂纹III-V外延
公开(公告)号：US20070054474A1
公开(公告)日：2007-03-08
申请号：US11209295
申请日：2005-08-23
申请人： Clarence Tracy , Eric Johnson , Papu Maniar
发明人： Clarence Tracy , Eric Johnson , Papu Maniar
IPC分类号： H01L21/20
CPC分类号： H01L21/76251 , H01L21/02381 , H01L21/02461 , H01L21/02543 , H01L21/02546 , H01L21/02658
摘要： A method of forming III-V epitaxy on a germanium-on-insulator (GOI) substrate having a bonded layer and a handle substrate begins with measuring a lattice parameter of the bonded layer at a first temperature. The lattice parameter of the bonded layer, which is a function of a coefficient of thermal expansion (CTE) of the handle substrate, is then calculated at an epitaxial growth temperature. An epitaxial composition is selected from a class of III-V material for epitaxial growth overlying the bonded layer, wherein the selected epitaxial composition is adjusted to have a lattice parameter that approximates the calculated lattice parameter of the bonded layer at the epitaxial growth temperature. An epitaxial layer can then be grown over the bonded layer with use of the adjusted epitaxial composition, producing a substantially defect-free III-V epitaxial layer. Furthermore, an improved defectivity is claimed when the epitaxial layer's CTE is approximately similar to that of the handle substrate.
摘要翻译：在具有接合层和手柄基板的绝缘体上锗（GOI）基板上形成III-V外延的方法开始于在第一温度下测量接合层的晶格参数。然后在外延生长温度下计算作为处理衬底的热膨胀系数（CTE）的函数的接合层的晶格参数。外延组合物从一类III-V材料中选择，用于覆盖键合层的外延生长，其中所选择的外延组合物被调整为具有接近在外延生长温度下键合层的计算的晶格参数的晶格参数。然后可以使用调整的外延组合物在接合层上生长外延层，产生基本上无缺陷的III-V外延层。此外，当外延层的CTE与处理衬底的CTE大致相似时，要求改进的缺陷率。

5. 发明申请

US20070141740A1 METHOD FOR DAMAGE AVOIDANCE IN TRANSFERRING AN ULTRA-THIN LAYER OF CRYSTALLINE MATERIAL WITH HIGH CRYSTALLINE QUALITY 有权
标题翻译：用于传输具有高结晶质量的结晶材料的超薄层的损伤避免方法
公开(公告)号：US20070141740A1
公开(公告)日：2007-06-21
申请号：US11554847
申请日：2006-10-31
申请人： Nirmal Theodore , John Freeman , Clarence Tracy
发明人： Nirmal Theodore , John Freeman , Clarence Tracy
IPC分类号： H01L21/00
CPC分类号： H01L21/76254 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262
摘要： A method for damage avoidance in transferring a monocrystalline, thin layer from a first substrate onto a second substrate involves epitaxial growth of a sandwich structure with a strained epitaxial layer buried below a monocrystalline thin layer, and lift-off and transfer of the monocrystalline thin layer with the cleaving controlled to happen within the buried strained layer in conjunction with the introduction of hydrogen.
摘要翻译：将单晶薄层从第一衬底转移到第二衬底上的避免损伤的方法包括外延生长具有埋在单晶薄层之下的应变外延层的夹层结构，以及单晶薄层的剥离和转移结合氢的引入，可以在埋层应变层内进行裂开控制。

6. 发明申请

US20150050771A1 METHOD AND TOOL TO REVERSE THE CHARGES IN ANTI-REFLECTION FILMS USED FOR SOLAR CELL APPLICATIONS 有权
标题翻译：在用于太阳能电池应用的抗反射膜中反转电荷的方法和工具
公开(公告)号：US20150050771A1
公开(公告)日：2015-02-19
申请号：US14456477
申请日：2014-08-11
申请人： Vivek Sharma , Clarence Tracy
发明人： Vivek Sharma , Clarence Tracy
IPC分类号： H01L31/18 , H01L31/0216
CPC分类号： H01L31/02168 , H01L31/186 , Y02E10/50 , Y02P70/521
摘要： A method is provided for making a solar cell. The method includes providing a stack including a substrate, a barrier layer disposed on the substrate, and an anti-reflective layer disposed on the barrier layer, where the anti-reflective layer has charge centers. The method also includes generating a corona with a charging tool and contacting the anti-reflective layer with the corona thereby injecting charge into at least some of the charge centers in the anti-reflective layer. Ultra-violet illumination and temperature-based annealing may be used to modify the charge of the anti-reflective layer.
摘要翻译：提供了制造太阳能电池的方法。该方法包括提供包括衬底，设置在衬底上的阻挡层和设置在阻挡层上的抗反射层的堆叠，其中抗反射层具有充电中心。该方法还包括用充电工具产生电晕并使抗反射层与电晕接触，从而将电荷注入抗反射层中的至少一些电荷中心。可以使用紫外照明和基于温度的退火来改变抗反射层的电荷。

7. 发明授权

US09559222B2 Method and tool to reverse the charges in anti-reflection films used for solar cell applications 有权
标题翻译：反向用于太阳能电池应用的抗反射膜中的电荷的方法和工具
公开(公告)号：US09559222B2
公开(公告)日：2017-01-31
申请号：US14456477
申请日：2014-08-11
申请人： Vivek Sharma , Clarence Tracy
发明人： Vivek Sharma , Clarence Tracy
IPC分类号： H01L31/0216 , H01L31/18
CPC分类号： H01L31/02168 , H01L31/186 , Y02E10/50 , Y02P70/521
摘要： A method is provided for making a solar cell. The method includes providing a stack including a substrate, a barrier layer disposed on the substrate, and an anti-reflective layer disposed on the barrier layer, where the anti-reflective layer has charge centers. The method also includes generating a corona with a charging tool and contacting the anti-reflective layer with the corona thereby injecting charge into at least some of the charge centers in the anti-reflective layer. Ultra-violet illumination and temperature-based annealing may be used to modify the charge of the anti-reflective layer.
摘要翻译：提供了制造太阳能电池的方法。该方法包括提供包括衬底，设置在衬底上的阻挡层和设置在阻挡层上的抗反射层的堆叠，其中抗反射层具有充电中心。该方法还包括用充电工具产生电晕并使抗反射层与电晕接触，从而将电荷注入抗反射层中的至少一些电荷中心。可以使用紫外照明和基于温度的退火来改变抗反射层的电荷。

8. 发明申请

US20070173040A1 Method of reducing an inter-atomic bond strength in a substance 审中-公开
标题翻译：减少物质中原子间键合强度的方法
公开(公告)号：US20070173040A1
公开(公告)日：2007-07-26
申请号：US11329324
申请日：2006-01-09
申请人： Nirmal Theodore , Stephen Schauer , Clarence Tracy
发明人： Nirmal Theodore , Stephen Schauer , Clarence Tracy
IPC分类号： H01L21/20
CPC分类号： H01L21/2636 , H01L21/02532 , H01L21/02689
摘要： A method of reducing an inter-atomic bond strength in a substance includes the steps of: providing a target material (110, 910, 1210, 1260, 1410, 1460); exposing the target material to a particle flood (140); and annealing the target material while exposing the target material to the particle flood. As an example, the target material can be a collection of non-activated dopant atoms within a semiconducting material. As another example, the target material can be a semiconducting material in an amorphous form. In a different embodiment of the invention an electrically conducting material (950, 1250, 1270, 1450, 1470, 1480) is used as an electron source rather than a particle flood, and an electrically conducting diffusion barrier (940) is placed between the electrically conducting material and the target material.
摘要翻译：减少物质中的原子间键合强度的方法包括以下步骤：提供目标材料（110,910,1210,1260,1410,1460）; 将目标材料暴露于颗粒溢流（140）; 并且在将目标材料暴露于颗粒物溢出的同时退火目标材料。作为示例，目标材料可以是半导体材料内的非活化掺杂剂原子的集合。作为另一个实例，靶材料可以是无定形形式的半导体材料。在本发明的不同实施例中，使用导电材料（950,1250,1270,1450,1470,1480）作为电子源而不是粒子泛流，并且导电扩散阻挡层（940）被放置在电导电材料和目标材料。

9. 发明申请

US20060216934A1 Conducting metal oxide with additive as p-MOS device electrode 有权
标题翻译：用添加剂将金属氧化物导电为p-MOS器件电极
公开(公告)号：US20060216934A1
公开(公告)日：2006-09-28
申请号：US11092469
申请日：2005-03-28
申请人： Yong Liang , Clarence Tracy
发明人： Yong Liang , Clarence Tracy
IPC分类号： H01L21/20
CPC分类号： H01L21/32051 , H01L21/28194 , H01L29/513 , H01L29/517
摘要： Methods for fabricating high work function p-MOS device metal electrodes are provided. In one embodiment, a method is provided for producing a metal electrode including the steps of: providing a high k dielectric stack with an exposed surface; contacting the exposed surface of the high k dielectric stack with a vapor of a metal oxide wherein the metal oxide is selected from the group consisting of RuOx, IrOx, ReOx, MoOx, WOx, VOx, and PdOx; and contacting the exposed surface of the dielectric stack with a vapor of an additive selected from the group consisting of SiO2, Al2O3, HfO2, ZrO2, MgO, SrO, BaO, Y2O3, La2O3, and TiO2, whereby contacting the exposed surface of the dielectric stack with the vapor of the metal oxide and the vapor of the additive forms an electrode and wherein the additive is present at an amount between about 1% to about 50% by atomic weight percent in the electrode.
摘要翻译：提供制造高功函数p-MOS器件金属电极的方法。在一个实施例中，提供了一种用于制造金属电极的方法，包括以下步骤：提供具有暴露表面的高k电介质叠层; 使高k电介质堆叠的暴露表面与金属氧化物的蒸气接触，其中金属氧化物选自RuO x，IrO x，ReO， x，x，x，x，x，x 2，x 2，x 2，x 2，x 2，x 2，以及使所述电介质堆叠的所述暴露表面与选自由SiO 2，Al 2 O 3 3，N 2 O 3， HfO 2，ZrO 2，MgO，SrO，BaO，Y 2 O 3，La 2 由此使电介质堆叠的暴露表面与金属氧化物的蒸气和添加剂的蒸气接触形成电极并且其中所述添加剂以所述电极中原子量的约1％至约50％之间的量存在。

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