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1. 发明授权

US06271555B1 Borderless wordline for DRAM cell 失效
标题翻译： DRAM单元的无边界字线
公开(公告)号：US06271555B1
公开(公告)日：2001-08-07
申请号：US09052403
申请日：1998-03-31
申请人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Wendell P. Noble, Jr.
IPC分类号： H01L27108
CPC分类号： H01L27/10873 , H01L27/10891 , Y10S257/905 , Y10S257/907 , Y10S257/908
摘要： A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline. A bitline contact contacts the source/drain region and the insulating material surrounding the active wordline to thereby make the bitline contact borderless to the wordline. A fully encased passing wordline is also provided which is spaced from and insulated from the segment gate conductor and the active wordline.
摘要翻译：公开了一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还具有具有源/漏区的单晶半导体衬底。主动导电字线沉积在分段栅极导体的顶部并与其电接触，该字线是具有顶部和侧壁的导电材料。电绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。围绕有源字线的绝缘材料包括覆盖顶部并且围绕其侧壁的一部分的氮化硅，并且二氧化硅围绕有源字线的侧壁的其余部分。位线触点接触源极/漏极区域和围绕有源字线的绝缘材料，从而使位线接触到字线。还提供了完全封装的通过字线，其与分段栅极导体和有源字线间隔开并与之隔绝。

2. 发明授权

US6121128A Method for making borderless wordline for DRAM cell 失效
标题翻译：为DRAM单元制作无边界字线的方法
公开(公告)号：US6121128A
公开(公告)日：2000-09-19
申请号：US398659
申请日：1999-09-17
申请人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Wendell P. Noble, Jr.
IPC分类号： H01L21/8242 , H01L21/4763
CPC分类号： H01L27/10873 , H01L27/10891 , Y10S257/905 , Y10S257/907 , Y10S257/908
摘要： A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline. A bitline contact contacts the source/drain region and the insulating material surrounding the active wordline to thereby make the bitline contact borderless to the wordline. A fully encased passing wordline is also provided which is spaced from and insulated from the segment gate conductor and the active wordline.
摘要翻译：公开了一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还具有具有源/漏区的单晶半导体衬底。主动导电字线沉积在分段栅极导体的顶部并与其电接触，该字线是具有顶部和侧壁的导电材料。电绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。围绕有源字线的绝缘材料包括覆盖顶部并且围绕其侧壁的一部分的氮化硅，并且二氧化硅围绕有源字线的侧壁的其余部分。位线触点接触源极/漏极区域和围绕有源字线的绝缘材料，从而使位线接触到字线。还提供了完全封装的通过字线，其与分段栅极导体和有源字线间隔开并与之隔绝。

3. 发明授权

US06261933B1 Process for building borderless bitline, wordline amd DRAM structure 失效
标题翻译：构建无边界位线，字线amd DRAM结构的过程
公开(公告)号：US06261933B1
公开(公告)日：2001-07-17
申请号：US09494415
申请日：2000-01-31
申请人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
IPC分类号： H01L213205
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10829 , H01L27/10861 , H01L27/10873 , H01L27/10891
摘要： It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the wordline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material. Insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. A bitline contact contacting the insulating material surrounds the wordline contact in the source/drain region to thereby make the bitline contact borderless to the wordline.
摘要翻译：本发明的一个特征是，最小尺寸字线连接大致最小尺寸的单独栅极段，位线接触与字线无边界。本发明的另一个目的是提供具有单独的段栅极导体以及具有位线接触对该字线无边界的极小尺寸的栅极连接器。一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还包括具有源/漏区的单晶半导体衬底。活动导电字线沉积在分段栅极导体的顶部并且电接触，其中字线是导电材料。绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。接触绝缘材料的位线接触器围绕源极/漏极区域中的字线触点，从而使位线接触到字线。

4. 发明授权

US06420748B1 Borderless bitline and wordline DRAM structure 失效
标题翻译：无边界位线和字线DRAM结构
公开(公告)号：US06420748B1
公开(公告)日：2002-07-16
申请号：US09657968
申请日：2000-09-08
申请人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
IPC分类号： H01L27108
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10829 , H01L27/10861 , H01L27/10873 , H01L27/10891
摘要： It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the wordline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material. Insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. A bitline contact contacting the insulating material surrounds the wordline contact in the source/drain region to thereby make the bitline contact borderless to the wordline.
摘要翻译：本发明的一个特征是，最小尺寸字线连接大致最小尺寸的单独栅极段，位线接触与字线无边界。本发明的另一个目的是提供具有单独的段栅极导体以及具有位线接触对该字线无边界的极小尺寸的栅极连接器。一种半导体结构及其制造方法，其包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还包括具有源/漏区的单晶半导体衬底。活动导电字线沉积在分段栅极导体的顶部并且电接触，其中字线是导电材料。绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。接触绝缘材料的位线接触器围绕源极/漏极区域中的字线触点，从而使位线接触到字线。

5. 发明授权

US06175128B1 Process for building borderless bitline, wordline and DRAM structure and resulting structure 失效
标题翻译：构建无边界位线，字线和DRAM结构以及结构的过程
公开(公告)号：US06175128B1
公开(公告)日：2001-01-16
申请号：US09052538
申请日：1998-03-31
申请人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
发明人： Mark C. Hakey , David V. Horak , William H. Ma , Wendell P. Noble, Jr.
IPC分类号： H01L27108
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10829 , H01L27/10861 , H01L27/10873 , H01L27/10891
摘要： It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the worldline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material. Insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. A bitline contact contacting the insulating material surrounds the wordline contact in the source/drain region to thereby make the bitline contact borderless to the wordline.
摘要翻译：本发明的一个特征是，极小维度字线将大致最小维度单独的门段链接到位线接触与世界线无边界。本发明的另一个目的是提供一种具有单独的段栅极导体和一个极小尺寸的栅极连接器的晶体管，其中位线接触与字线无边界。一种半导体结构及其制造方法，包括具有包括栅极的晶体管的DRAM单元。栅极包括在薄介电材料上的诸如多晶硅的栅极导体的单独段。晶体管还包括具有源/漏区的单晶半导体衬底。活动导电字线沉积在分段栅极导体的顶部并且电接触，其中字线是导电材料。绝缘材料完全围绕有源字线，除了有源字线接触分段栅极导体之外。接触绝缘材料的位线接触器围绕源极/漏极区域中的字线触点，从而使位线接触到字线。

6. 发明授权

US08039334B2 Shared gate for conventional planar device and horizontal CNT 有权
标题翻译：常规平面器件和水平CNT的共用门
公开(公告)号：US08039334B2
公开(公告)日：2011-10-18
申请号：US12902944
申请日：2010-10-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

7. 发明授权

US08004024B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08004024B2
公开(公告)日：2011-08-23
申请号：US12348404
申请日：2009-01-05
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
摘要翻译：晶体管。晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

8. 发明授权

US07922796B2 Chemical and particulate filters containing chemically modified carbon nanotube structures 失效
标题翻译：包含化学改性碳纳米管结构的化学和微粒过滤器
公开(公告)号：US07922796B2
公开(公告)日：2011-04-12
申请号：US12652908
申请日：2010-01-06
申请人： Steven J. Holmes , Mark C. Hakey , David V. Horak , James G. Ryan
发明人： Steven J. Holmes , Mark C. Hakey , David V. Horak , James G. Ryan
IPC分类号： B01D59/26
CPC分类号： B01D53/02 , B01D2253/102 , B01D2253/304 , B01J20/20 , B01J20/205 , B01J20/3242 , B82Y30/00 , Y10S55/05 , Y10S977/742 , Y10S977/745 , Y10S977/748 , Y10S977/75 , Y10S977/752
摘要： A carbon nanotube filter. The filter including a filter housing; and chemically active carbon nanotubes within the filter housing, the chemically active carbon nanotubes comprising a chemically active layer formed on carbon nanotubes or comprising chemically reactive groups on sidewalls of the carbon nanotubes; and media containing the chemically active carbon nanotubes.
摘要翻译：碳纳米管过滤器。过滤器包括过滤器壳体; 和化学活性碳纳米管，所述化学活性碳纳米管包括在碳纳米管上形成的化学活性层或在碳纳米管的侧壁上包含化学反应性基团; 和含有化学活性碳纳米管的介质。

9. 发明授权

US07557023B2 Implantation of gate regions in semiconductor device fabrication 失效
标题翻译：在半导体器件制造中植入栅极区域
公开(公告)号：US07557023B2
公开(公告)日：2009-07-07
申请号：US11532189
申请日：2006-09-15
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/425
CPC分类号： H01L29/66545 , H01L21/0273 , H01L21/266 , H01L21/28035 , H01L29/1083 , H01L29/6653 , H01L29/6659
摘要： A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.
摘要翻译：半导体制造方法。该方法包括提供半导体结构，其包括（i）半导体层，（ii）半导体层上的栅极电介质层，以及（iii）栅极电介质层上的栅电极区。栅极电介质层被夹在半导体层和栅极电极区域之间并使其电绝缘。半导体层和栅极介电层共享公共接口表面，其界定垂直于公共接口表面的参考方向并且从半导体层指向栅极介电层。接下来，在栅极电介质层和栅极电极区域上形成抗蚀剂层。接下来，去除在参考方向上正好在栅极区域上方的抗蚀剂层的盖部分，而不去除在参考方向上不在栅电极区域正上方的任何部分的抗蚀剂层。

10. 发明申请

US20090087795A1 METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM 失效
标题翻译：用于在浸没层析系统中清洁半导体衬底的方法和装置
公开(公告)号：US20090087795A1
公开(公告)日：2009-04-02
申请号：US12045290
申请日：2008-03-10
申请人： Steven J. Holmes , Mark C. Hakey , Toshiharu Furukawa , David V. Horak
发明人： Steven J. Holmes , Mark C. Hakey , Toshiharu Furukawa , David V. Horak
IPC分类号： G03F7/20
CPC分类号： G03F7/70341 , G03F7/70925
摘要： A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or including a cleaning mechanism in a cleaning station of an immersion lithographic system.
摘要翻译：一种用于减少和防止残留物形成和去除在浸没式光刻工具中形成的残留物的方法和装置。该设备包括在浸没式光刻系统的浸没头部内并入清洁机构，或者在浸没式光刻系统的清洁站中包括清洁机构。

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