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1. 发明授权

US06893947B2 Advanced RF enhancement-mode FETs with improved gate properties 有权
标题翻译：先进的RF增强型FET，具有改进的栅极性能
公开(公告)号：US06893947B2
公开(公告)日：2005-05-17
申请号：US10179769
申请日：2002-06-25
申请人： Marino J. Martinez , Ernest Schirmann , Olin L. Hartin , Colby G. Rampley , Mariam G. Sadaka , Charles E. Weitzel , Julio Costa
发明人： Marino J. Martinez , Ernest Schirmann , Olin L. Hartin , Colby G. Rampley , Mariam G. Sadaka , Charles E. Weitzel , Julio Costa
IPC分类号： H01L21/285 , H01L21/337 , H01L29/80 , H01L21/22
CPC分类号： H01L29/66924 , H01L21/28587 , H01L29/802
摘要： A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.
摘要翻译：提供了一种制造具有改进的栅极特性的RF增强型FET（30）的方法。该方法包括以下步骤：提供（131）具有形成在其上的半导体层（32-35）的堆叠的衬底（31），所述堆叠包括限定器件沟道的覆盖层（35）和中心层（33）在所述盖层上形成（103）光致抗蚀剂图案（58），由此限定掩蔽区域和未掩蔽区域，并且以任何顺序，（a）在所述未掩蔽区域中产生（105）植入区域（36,37），和（b）从未掩蔽区域移除（107）盖层。通过不重叠地形成注入区域和盖子区域，可以实现具有低电流泄漏的装置。

2. 发明授权

US08440539B2 Isolation trench processing for strain control 有权
标题翻译：用于应变控制的隔离槽加工
公开(公告)号：US08440539B2
公开(公告)日：2013-05-14
申请号：US11831400
申请日：2007-07-31
申请人： Mariam G. Sadaka , Michael A. Mendicino
发明人： Mariam G. Sadaka , Michael A. Mendicino
IPC分类号： H01L21/762
CPC分类号： H01L21/76205 , H01L29/78 , H01L29/7846
摘要： A semiconductor fabrication process includes forming a hard mask, e.g., silicon nitride, over an active layer of a silicon on insulator (SOI) wafer, removing a portion of the hard mask and the active layer to form a trench, and forming an isolation dielectric in the trench where the dielectric exerts compressive strain on a channel region of the active layer. Forming the dielectric may include performing a thermal oxidation. Before performing the thermal oxidation, semiconductor structures may be formed, e.g., by epitaxy, on sidewalls of the trench. The structures may be silicon or a silicon compound, e.g., silicon germanium. During the thermal oxidation, the semiconductor structures are consumed. In the case of a silicon germanium, the germanium may diffuse during the thermal oxidation to produce a silicon germanium channel region.
摘要翻译：半导体制造工艺包括在绝缘体上硅（SOI）晶片的有源层上形成例如氮化硅的硬掩模，去除硬掩模和有源层的一部分以形成沟槽，以及形成隔离电介质在沟槽中，电介质在有源层的沟道区上施加压应变。形成电介质可以包括进行热氧化。在进行热氧化之前，半导体结构可以例如通过外延形成在沟槽的侧壁上。该结构可以是硅或硅化合物，例如硅锗。在热氧化期间，半导体结构被消耗。在硅锗的情况下，锗可以在热氧化期间扩散以产生硅锗通道区。

3. 发明授权

US07544548B2 Trench liner for DSO integration 失效
标题翻译：用于DSO集成的沟槽衬垫
公开(公告)号：US07544548B2
公开(公告)日：2009-06-09
申请号：US11443628
申请日：2006-05-31
申请人： Mariam G. Sadaka , Ted R. White , Bich-Yen Nguyen
发明人： Mariam G. Sadaka , Ted R. White , Bich-Yen Nguyen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823878 , H01L21/823807 , H01L21/84
摘要： A semiconductor process and apparatus provide a shallow trench isolation region (96) with a trench liner (95, 104) for use in a hybrid substrate device (21) by lining a first trench with a first trench liner (95), and then lining a second trench formed within the first trench by depositing a second trench liner (104) that is anisotropically etched to expose an underlying substrate (70) on which is epitaxially grown a silicon layer (110) to fill the second trench. By forming first gate electrodes (251) over a first SOI substrate (90) using deposited (100) silicon and forming second gate electrodes (261) over an epitaxially grown (110) silicon substrate (110), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (261) having improved hole mobility.
摘要翻译：半导体工艺和装置提供具有沟槽衬垫（95,104）的浅沟槽隔离区（96），用于混合衬底器件（21），用于通过用第一沟槽衬垫（95）衬里第一沟槽，然后衬里通过沉积第二沟槽衬垫（104）形成第一沟槽内的第二沟槽，所述第二沟槽衬垫（104）被各向异性蚀刻以暴露其上外延生长硅衬底（110）以填充第二沟槽的下面的衬底（70）。通过使用沉积的（100）硅并在外延生长（110）硅衬底（110）上形成第二栅电极（261）在第一SOI衬底（90）上形成第一栅电极（251），获得高性能CMOS器件其包括具有改善的空穴迁移率的高k金属PMOS栅电极（261）。

4. 发明授权

US07265004B2 Electronic devices including a semiconductor layer and a process for forming the same 有权
标题翻译：包括半导体层的电子器件及其形成方法
公开(公告)号：US07265004B2
公开(公告)日：2007-09-04
申请号：US11273092
申请日：2005-11-14
申请人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
发明人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
摘要翻译：电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

5. 发明授权

US07226833B2 Semiconductor device structure and method therefor 有权
标题翻译：半导体器件结构及其方法
公开(公告)号：US07226833B2
公开(公告)日：2007-06-05
申请号：US10977423
申请日：2004-10-29
申请人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
发明人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
IPC分类号： H01L21/8234
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

6. 发明授权

US07056778B2 Semiconductor layer formation 失效
标题翻译：半导体层形成
公开(公告)号：US07056778B2
公开(公告)日：2006-06-06
申请号：US10919784
申请日：2004-08-17
申请人： Chun-Li Liu , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White , Qianghua Xie
发明人： Chun-Li Liu , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White , Qianghua Xie
IPC分类号： H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在加热晶片的同时使含氯气体（例如氯化氢，氯气，四氯化碳和三氯乙烷）流过晶片。在一个实例中，在用作形成应变半导体层（例如应变硅）的模板层的半导体层上的冷凝过程中，含有轴承气体流动。在其他实例中，在冷凝操作之后，在晶片的后烘烤期间，含氯气体流动。

7. 发明授权

US07821067B2 Electronic devices including a semiconductor layer 有权
标题翻译：包括半导体层的电子器件
公开(公告)号：US07821067B2
公开(公告)日：2010-10-26
申请号：US11836844
申请日：2007-08-10
申请人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
发明人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
摘要翻译：电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

8. 发明授权

US07700420B2 Integrated circuit with different channel materials for P and N channel transistors and method therefor 有权
标题翻译：用于P和N沟道晶体管的不同沟道材料的集成电路及其方法
公开(公告)号：US07700420B2
公开(公告)日：2010-04-20
申请号：US11402395
申请日：2006-04-12
申请人： Voon-Yew Thean , Bich-Yen Nguyen , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White
发明人： Voon-Yew Thean , Bich-Yen Nguyen , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8258 , H01L27/1203
摘要： A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type transistor) is formed in and on the first semiconductor layer. The III-nitride layer may be indium nitride. In the first region, the substrate may include a second semiconductor layer, a graded transition layer over the second semiconductor layer, and a buffer layer over the transition layer, where the III-nitride layer is over the buffer layer. In the second region, the substrate may include the second semiconductor layer and an insulating layer over the second semiconductor layer, where the first semiconductor layer is over the insulating layer.
摘要翻译：衬底包括第一区域和第二区域。第一区域包括III族氮化物层，第二区域包括第一半导体层。在III族氮化物层上形成第一晶体管（例如n型晶体管），并且在第一半导体层上形成第二晶体管（例如p型晶体管）。 III族氮化物层可以是氮化铟。在第一区域中，衬底可以包括第二半导体层，在第二半导体层上的渐变过渡层，以及过渡层上的缓冲层，其中III族氮化物层在缓冲层之上。在第二区域中，衬底可以包括第二半导体层和在第二半导体层上的绝缘层，其中第一半导体层在绝缘层之上。

9. 发明授权

US07419866B2 Process of forming an electronic device including a semiconductor island over an insulating layer 有权
标题翻译：在绝缘层上形成包括半导体岛的电子器件的工艺
公开(公告)号：US07419866B2
公开(公告)日：2008-09-02
申请号：US11375893
申请日：2006-03-15
申请人： Mariam G. Sadaka , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam G. Sadaka , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/8238
CPC分类号： H01L21/32 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/84
摘要： A process of forming an electronic device can include forming a patterned oxidation-resistant layer over a semiconductor layer that overlies a substrate, and patterning the semiconductor layer to form a semiconductor island. The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.
摘要翻译：形成电子器件的方法可以包括在覆盖在衬底上的半导体层上形成图案化的抗氧化层，并且图案化半导体层以形成半导体岛。半导体岛包括与第一表面相对的第一表面和第二表面，并且第一表面与第二表面相比更靠近基底。该方法还可以包括沿着半导体岛的一侧形成耐氧化材料或者沿半导体岛的一侧选择性地沉积半导体材料。该方法还可以包括将图案化的抗氧化层和半导体岛暴露于含氧环境中，其中沿着第一表面的半导体岛的第一部分在曝光图案化的抗氧化层，半导体岛，并将抗氧化材料转化为含氧环境。

10. 发明授权

US07378306B2 Selective silicon deposition for planarized dual surface orientation integration 有权
标题翻译：用于平面化双面取向积分的选择性硅沉积
公开(公告)号：US07378306B2
公开(公告)日：2008-05-27
申请号：US11375763
申请日：2006-03-14
申请人： Gregory S. Spencer , Peter J. Beckage , Mariam G. Sadaka , Veer Dhandapani
发明人： Gregory S. Spencer , Peter J. Beckage , Mariam G. Sadaka , Veer Dhandapani
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (225) having a more uniform polish surface (300) by thickening an SOI semiconductor layer (210) in relation to a previously or subsequently formed epitaxial silicon layer (220) with a selective silicon deposition process that covers the SOI semiconductor layer (210) with a crystalline semiconductor layer (216). By forming first gate electrodes (151) over a first SOI substrate (90) using deposited (100) silicon and forming second gate electrodes (161) over an epitaxially grown (110) silicon substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.
摘要翻译：半导体工艺和设备通过使用选择性硅沉积物相对于先前或随后形成的外延硅层（220）增厚SOI半导体层（210）来提供具有更均匀的抛光表面（300）的平坦化的混合衬底（225）用SOI晶体半导体层（216）覆盖SOI半导体层（210）的工艺。通过使用沉积（100）硅并在外延生长（110）硅衬底（70）上形成第二栅电极（161）在第一SOI衬底（90）上形成第一栅电极（151），获得高性能CMOS器件其包括具有改善的空穴迁移率的高k金属PMOS栅电极（161）。

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